1 /* 2 * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A720_H 8 #define CORTEX_A720_H 9 10 #define CORTEX_A720_MIDR U(0x410FD810) 11 12 /* Cortex A720 loop count for CVE-2022-23960 mitigation */ 13 #define CORTEX_A720_BHB_LOOP_COUNT U(38) 14 15 /******************************************************************************* 16 * CPU Auxiliary Control register 1 specific definitions. 17 ******************************************************************************/ 18 #define CORTEX_A720_CPUACTLR_EL1 S3_0_C15_C1_0 19 20 /******************************************************************************* 21 * CPU Auxiliary Control register 2 specific definitions. 22 ******************************************************************************/ 23 #define CORTEX_A720_CPUACTLR2_EL1 S3_0_C15_C1_1 24 25 /******************************************************************************* 26 * CPU Auxiliary Control register 4 specific definitions. 27 ******************************************************************************/ 28 #define CORTEX_A720_CPUACTLR4_EL1 S3_0_C15_C1_3 29 30 /******************************************************************************* 31 * CPU Extended Control register specific definitions 32 ******************************************************************************/ 33 #define CORTEX_A720_CPUECTLR_EL1 S3_0_C15_C1_4 34 35 /******************************************************************************* 36 * CPU Power Control register specific definitions 37 ******************************************************************************/ 38 #define CORTEX_A720_CPUPWRCTLR_EL1 S3_0_C15_C2_7 39 #define CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 40 41 /******************************************************************************* 42 * CPU Instruction Patching Register Definitions 43 ******************************************************************************/ 44 #define CORTEX_A720_CPUPSELR_EL3 S3_6_C15_C8_0 45 #define CORTEX_A720_CPUPCR_EL3 S3_6_C15_C8_1 46 #define CORTEX_A720_CPUPOR_EL3 S3_6_C15_C8_2 47 #define CORTEX_A720_CPUPMR_EL3 S3_6_C15_C8_3 48 49 #ifndef __ASSEMBLER__ 50 long check_erratum_cortex_a720_3699561(long cpu_rev); 51 #endif /* __ASSEMBLER__ */ 52 53 #endif /* CORTEX_A720_H */ 54