131b39455SGovindraj Raja /* 2050c4a38SGovindraj Raja * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 331b39455SGovindraj Raja * 431b39455SGovindraj Raja * SPDX-License-Identifier: BSD-3-Clause 531b39455SGovindraj Raja */ 631b39455SGovindraj Raja 731b39455SGovindraj Raja #ifndef CORTEX_A720_H 831b39455SGovindraj Raja #define CORTEX_A720_H 931b39455SGovindraj Raja 1031b39455SGovindraj Raja #define CORTEX_A720_MIDR U(0x410FD810) 1131b39455SGovindraj Raja 1231b39455SGovindraj Raja /******************************************************************************* 13152f4cfaSBipin Ravi * CPU Auxiliary Control register 1 specific definitions. 14152f4cfaSBipin Ravi ******************************************************************************/ 15152f4cfaSBipin Ravi #define CORTEX_A720_CPUACTLR_EL1 S3_0_C15_C1_0 16152f4cfaSBipin Ravi 17152f4cfaSBipin Ravi /******************************************************************************* 187385213eSBipin Ravi * CPU Auxiliary Control register 2 specific definitions. 197385213eSBipin Ravi ******************************************************************************/ 207385213eSBipin Ravi #define CORTEX_A720_CPUACTLR2_EL1 S3_0_C15_C1_1 217385213eSBipin Ravi 227385213eSBipin Ravi /******************************************************************************* 2312140908SSona Mathew * CPU Auxiliary Control register 4 specific definitions. 2412140908SSona Mathew ******************************************************************************/ 2512140908SSona Mathew #define CORTEX_A720_CPUACTLR4_EL1 S3_0_C15_C1_3 2612140908SSona Mathew 2712140908SSona Mathew /******************************************************************************* 2831b39455SGovindraj Raja * CPU Extended Control register specific definitions 2931b39455SGovindraj Raja ******************************************************************************/ 3031b39455SGovindraj Raja #define CORTEX_A720_CPUECTLR_EL1 S3_0_C15_C1_4 3131b39455SGovindraj Raja 3231b39455SGovindraj Raja /******************************************************************************* 3331b39455SGovindraj Raja * CPU Power Control register specific definitions 3431b39455SGovindraj Raja ******************************************************************************/ 3531b39455SGovindraj Raja #define CORTEX_A720_CPUPWRCTLR_EL1 S3_0_C15_C2_7 3631b39455SGovindraj Raja #define CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 3731b39455SGovindraj Raja 38*87e69a8fSJohn Powell /******************************************************************************* 39*87e69a8fSJohn Powell * CPU Instruction Patching Register Definitions 40*87e69a8fSJohn Powell ******************************************************************************/ 41*87e69a8fSJohn Powell #define CORTEX_A720_CPUPSELR_EL3 S3_6_C15_C8_0 42*87e69a8fSJohn Powell #define CORTEX_A720_CPUPCR_EL3 S3_6_C15_C8_1 43*87e69a8fSJohn Powell #define CORTEX_A720_CPUPOR_EL3 S3_6_C15_C8_2 44*87e69a8fSJohn Powell #define CORTEX_A720_CPUPMR_EL3 S3_6_C15_C8_3 45*87e69a8fSJohn Powell 46050c4a38SGovindraj Raja #ifndef __ASSEMBLER__ 47050c4a38SGovindraj Raja long check_erratum_cortex_a720_3699561(long cpu_rev); 48050c4a38SGovindraj Raja #endif /* __ASSEMBLER__ */ 49050c4a38SGovindraj Raja 5031b39455SGovindraj Raja #endif /* CORTEX_A720_H */ 51