1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CORTEX_A72_H__ 8 #define __CORTEX_A72_H__ 9 #include <utils_def.h> 10 11 /* Cortex-A72 midr for revision 0 */ 12 #define CORTEX_A72_MIDR 0x410FD080 13 14 /******************************************************************************* 15 * CPU Extended Control register specific definitions. 16 ******************************************************************************/ 17 #define CORTEX_A72_ECTLR_EL1 S3_1_C15_C2_1 18 19 #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6) 20 #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) 21 #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) 22 #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) 23 24 /******************************************************************************* 25 * CPU Memory Error Syndrome register specific definitions. 26 ******************************************************************************/ 27 #define CORTEX_A72_MERRSR_EL1 S3_1_C15_C2_2 28 29 /******************************************************************************* 30 * CPU Auxiliary Control register specific definitions. 31 ******************************************************************************/ 32 #define CORTEX_A72_CPUACTLR_EL1 S3_1_C15_C2_0 33 34 #define CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) 35 #define CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55) 36 #define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) 37 #define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) 38 #define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) 39 40 /******************************************************************************* 41 * L2 Auxiliary Control register specific definitions. 42 ******************************************************************************/ 43 #define CORTEX_A72_L2ACTLR_EL1 S3_1_C15_C0_0 44 45 #define CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN (ULL(1) << 14) 46 47 /******************************************************************************* 48 * L2 Control register specific definitions. 49 ******************************************************************************/ 50 #define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2 51 52 #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 53 #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 54 55 #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 56 #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1 57 #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 58 59 /******************************************************************************* 60 * L2 Memory Error Syndrome register specific definitions. 61 ******************************************************************************/ 62 #define CORTEX_A72_L2MERRSR_EL1 S3_1_C15_C2_3 63 64 #endif /* __CORTEX_A72_H__ */ 65