115889d13SHarrison Mutai /* 226437afdSGovindraj Raja * Copyright (c) 2021-2025, Arm Limited. All rights reserved. 315889d13SHarrison Mutai * 415889d13SHarrison Mutai * SPDX-License-Identifier: BSD-3-Clause 515889d13SHarrison Mutai */ 615889d13SHarrison Mutai 715889d13SHarrison Mutai #ifndef CORTEX_A715_H 815889d13SHarrison Mutai #define CORTEX_A715_H 915889d13SHarrison Mutai 1015889d13SHarrison Mutai #define CORTEX_A715_MIDR U(0x410FD4D0) 1115889d13SHarrison Mutai 1215889d13SHarrison Mutai /* Cortex-A715 loop count for CVE-2022-23960 mitigation */ 1315889d13SHarrison Mutai #define CORTEX_A715_BHB_LOOP_COUNT U(38) 1415889d13SHarrison Mutai 1515889d13SHarrison Mutai /******************************************************************************* 16*fcf2ab71SJohn Powell * CPU Register Mappings 1715a04615SSona Mathew ******************************************************************************/ 18*fcf2ab71SJohn Powell #define CORTEX_A715_CPUCFR_EL1 S3_0_C15_C0_0 1915a04615SSona Mathew #define CORTEX_A715_CPUACTLR_EL1 S3_0_C15_C1_0 206a6b2823SBipin Ravi #define CORTEX_A715_CPUACTLR2_EL1 S3_0_C15_C1_1 21*fcf2ab71SJohn Powell #define CORTEX_A715_CPUACTLR3_EL1 S3_0_C15_C1_2 2215889d13SHarrison Mutai #define CORTEX_A715_CPUECTLR_EL1 S3_0_C15_C1_4 23*fcf2ab71SJohn Powell #define CORTEX_A715_CPUECTLR2_EL1 S3_0_C15_C1_5 2433c665aeSHarrison Mutai #define CORTEX_A715_CPUPSELR_EL3 S3_6_C15_C8_0 2533c665aeSHarrison Mutai #define CORTEX_A715_CPUPCR_EL3 S3_6_C15_C8_1 2633c665aeSHarrison Mutai #define CORTEX_A715_CPUPOR_EL3 S3_6_C15_C8_2 2733c665aeSHarrison Mutai #define CORTEX_A715_CPUPMR_EL3 S3_6_C15_C8_3 2833c665aeSHarrison Mutai 2915889d13SHarrison Mutai /******************************************************************************* 3015889d13SHarrison Mutai * CPU Power Control register specific definitions 3115889d13SHarrison Mutai ******************************************************************************/ 3215889d13SHarrison Mutai #define CORTEX_A715_CPUPWRCTLR_EL1 S3_0_C15_C2_7 3315889d13SHarrison Mutai #define CORTEX_A715_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 3415889d13SHarrison Mutai 3526437afdSGovindraj Raja #ifndef __ASSEMBLER__ 3626437afdSGovindraj Raja long check_erratum_cortex_a715_3699560(long cpu_rev); 3726437afdSGovindraj Raja #endif /* __ASSEMBLER__ */ 3826437afdSGovindraj Raja 3915889d13SHarrison Mutai #endif /* CORTEX_A715_H */ 40