1 /* 2 * Copyright (c) 2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A710_H 8 #define CORTEX_A710_H 9 10 #define CORTEX_A710_MIDR U(0x410FD470) 11 12 /******************************************************************************* 13 * CPU Extended Control register specific definitions 14 ******************************************************************************/ 15 #define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4 16 #define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8) 17 18 /******************************************************************************* 19 * CPU Power Control register specific definitions 20 ******************************************************************************/ 21 #define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7 22 #define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 23 24 /******************************************************************************* 25 * CPU Auxiliary Control register specific definitions. 26 ******************************************************************************/ 27 #define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0 28 #define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46) 29 #define CORTEX_A710_CPUACTLR_EL1_BIT_22 (ULL(1) << 22) 30 31 /******************************************************************************* 32 * CPU Auxiliary Control register specific definitions. 33 ******************************************************************************/ 34 #define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0 35 #define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13) 36 #define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44) 37 38 /******************************************************************************* 39 * CPU Auxiliary Control register specific definitions. 40 ******************************************************************************/ 41 #define CORTEX_A710_CPUECTLR2_EL1 S3_0_C15_C1_5 42 #define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9) 43 #define CPUECTLR2_EL1_PF_MODE_LSB U(11) 44 #define CPUECTLR2_EL1_PF_MODE_WIDTH U(4) 45 46 #endif /* CORTEX_A710_H */ 47