1 /* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A57_H 8 #define CORTEX_A57_H 9 10 #include <lib/utils_def.h> 11 12 /* Cortex-A57 midr for revision 0 */ 13 #define CORTEX_A57_MIDR U(0x410FD070) 14 15 /* Retention timer tick definitions */ 16 #define RETENTION_ENTRY_TICKS_2 U(0x1) 17 #define RETENTION_ENTRY_TICKS_8 U(0x2) 18 #define RETENTION_ENTRY_TICKS_32 U(0x3) 19 #define RETENTION_ENTRY_TICKS_64 U(0x4) 20 #define RETENTION_ENTRY_TICKS_128 U(0x5) 21 #define RETENTION_ENTRY_TICKS_256 U(0x6) 22 #define RETENTION_ENTRY_TICKS_512 U(0x7) 23 24 /******************************************************************************* 25 * CPU Extended Control register specific definitions. 26 ******************************************************************************/ 27 #define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1 28 29 #define CORTEX_A57_ECTLR_SMP_BIT (U(1) << 6) 30 #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (U(1) << 38) 31 #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (U(0x3) << 35) 32 #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (U(0x3) << 32) 33 34 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0) 35 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) 36 37 /******************************************************************************* 38 * CPU Memory Error Syndrome register specific definitions. 39 ******************************************************************************/ 40 #define CORTEX_A57_MERRSR_EL1 S3_1_C15_C2_2 41 42 /******************************************************************************* 43 * CPU Auxiliary Control register specific definitions. 44 ******************************************************************************/ 45 #define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0 46 47 #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59) 48 #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55) 49 #define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54) 50 #define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52) 51 #define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) 52 #define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) 53 #define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38) 54 #define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) 55 #define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27) 56 #define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25) 57 #define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) 58 59 /******************************************************************************* 60 * L2 Control register specific definitions. 61 ******************************************************************************/ 62 #define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2 63 64 #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) 65 #define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) 66 67 #define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) 68 #define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) 69 70 #define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21) 71 72 /******************************************************************************* 73 * L2 Extended Control register specific definitions. 74 ******************************************************************************/ 75 #define CORTEX_A57_L2ECTLR_EL1 S3_1_C11_C0_3 76 77 #define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0) 78 #define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) 79 80 /******************************************************************************* 81 * L2 Memory Error Syndrome register specific definitions. 82 ******************************************************************************/ 83 #define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3 84 85 #endif /* CORTEX_A57_H */ 86