1 /* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CORTEX_A57_H__ 8 #define __CORTEX_A57_H__ 9 10 /* Cortex-A57 midr for revision 0 */ 11 #define CORTEX_A57_MIDR U(0x410FD070) 12 13 /* Retention timer tick definitions */ 14 #define RETENTION_ENTRY_TICKS_2 U(0x1) 15 #define RETENTION_ENTRY_TICKS_8 U(0x2) 16 #define RETENTION_ENTRY_TICKS_32 U(0x3) 17 #define RETENTION_ENTRY_TICKS_64 U(0x4) 18 #define RETENTION_ENTRY_TICKS_128 U(0x5) 19 #define RETENTION_ENTRY_TICKS_256 U(0x6) 20 #define RETENTION_ENTRY_TICKS_512 U(0x7) 21 22 /******************************************************************************* 23 * CPU Extended Control register specific definitions. 24 ******************************************************************************/ 25 #define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1 26 27 #define CORTEX_A57_ECTLR_SMP_BIT (U(1) << 6) 28 #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (U(1) << 38) 29 #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (U(0x3) << 35) 30 #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (U(0x3) << 32) 31 32 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0) 33 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) 34 35 /******************************************************************************* 36 * CPU Memory Error Syndrome register specific definitions. 37 ******************************************************************************/ 38 #define CORTEX_A57_MERRSR_EL1 S3_1_C15_C2_2 39 40 /******************************************************************************* 41 * CPU Auxiliary Control register specific definitions. 42 ******************************************************************************/ 43 #define CORTEX_A57_ACTLR_EL1 S3_1_C15_C2_0 44 45 #define CORTEX_A57_ACTLR_DIS_LOAD_PASS_DMB (ULL(1) << 59) 46 #define CORTEX_A57_ACTLR_GRE_NGRE_AS_NGNRE (ULL(1) << 54) 47 #define CORTEX_A57_ACTLR_DIS_OVERREAD (ULL(1) << 52) 48 #define CORTEX_A57_ACTLR_NO_ALLOC_WBWA (ULL(1) << 49) 49 #define CORTEX_A57_ACTLR_DCC_AS_DCCI (ULL(1) << 44) 50 #define CORTEX_A57_ACTLR_FORCE_FPSCR_FLUSH (ULL(1) << 38) 51 #define CORTEX_A57_ACTLR_DIS_STREAMING (ULL(3) << 27) 52 #define CORTEX_A57_ACTLR_DIS_L1_STREAMING (ULL(3) << 25) 53 #define CORTEX_A57_ACTLR_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) 54 55 /******************************************************************************* 56 * L2 Control register specific definitions. 57 ******************************************************************************/ 58 #define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2 59 60 #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) 61 #define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) 62 63 #define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) 64 #define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) 65 66 #define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21) 67 68 /******************************************************************************* 69 * L2 Extended Control register specific definitions. 70 ******************************************************************************/ 71 #define CORTEX_A57_L2ECTLR_EL1 S3_1_C11_C0_3 72 73 #define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0) 74 #define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) 75 76 /******************************************************************************* 77 * L2 Memory Error Syndrome register specific definitions. 78 ******************************************************************************/ 79 #define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3 80 81 #endif /* __CORTEX_A57_H__ */ 82