1 /* 2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CORTEX_A57_H__ 8 #define __CORTEX_A57_H__ 9 #include <utils_def.h> 10 11 /* Cortex-A57 midr for revision 0 */ 12 #define CORTEX_A57_MIDR U(0x410FD070) 13 14 /* Retention timer tick definitions */ 15 #define RETENTION_ENTRY_TICKS_2 U(0x1) 16 #define RETENTION_ENTRY_TICKS_8 U(0x2) 17 #define RETENTION_ENTRY_TICKS_32 U(0x3) 18 #define RETENTION_ENTRY_TICKS_64 U(0x4) 19 #define RETENTION_ENTRY_TICKS_128 U(0x5) 20 #define RETENTION_ENTRY_TICKS_256 U(0x6) 21 #define RETENTION_ENTRY_TICKS_512 U(0x7) 22 23 /******************************************************************************* 24 * CPU Extended Control register specific definitions. 25 ******************************************************************************/ 26 #define CORTEX_A57_ECTLR_EL1 S3_1_C15_C2_1 27 28 #define CORTEX_A57_ECTLR_SMP_BIT (U(1) << 6) 29 #define CORTEX_A57_ECTLR_DIS_TWD_ACC_PFTCH_BIT (U(1) << 38) 30 #define CORTEX_A57_ECTLR_L2_IPFTCH_DIST_MASK (U(0x3) << 35) 31 #define CORTEX_A57_ECTLR_L2_DPFTCH_DIST_MASK (U(0x3) << 32) 32 33 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT U(0) 34 #define CORTEX_A57_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A57_ECTLR_CPU_RET_CTRL_SHIFT) 35 36 /******************************************************************************* 37 * CPU Memory Error Syndrome register specific definitions. 38 ******************************************************************************/ 39 #define CORTEX_A57_MERRSR_EL1 S3_1_C15_C2_2 40 41 /******************************************************************************* 42 * CPU Auxiliary Control register specific definitions. 43 ******************************************************************************/ 44 #define CORTEX_A57_CPUACTLR_EL1 S3_1_C15_C2_0 45 46 #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_DMB (ULL(1) << 59) 47 #define CORTEX_A57_CPUACTLR_EL1_DIS_LOAD_PASS_STORE (ULL(1) << 55) 48 #define CORTEX_A57_CPUACTLR_EL1_GRE_NGRE_AS_NGNRE (ULL(1) << 54) 49 #define CORTEX_A57_CPUACTLR_EL1_DIS_OVERREAD (ULL(1) << 52) 50 #define CORTEX_A57_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49) 51 #define CORTEX_A57_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44) 52 #define CORTEX_A57_CPUACTLR_EL1_FORCE_FPSCR_FLUSH (ULL(1) << 38) 53 #define CORTEX_A57_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32) 54 #define CORTEX_A57_CPUACTLR_EL1_DIS_STREAMING (ULL(3) << 27) 55 #define CORTEX_A57_CPUACTLR_EL1_DIS_L1_STREAMING (ULL(3) << 25) 56 #define CORTEX_A57_CPUACTLR_EL1_DIS_INDIRECT_PREDICTOR (ULL(1) << 4) 57 58 /******************************************************************************* 59 * L2 Control register specific definitions. 60 ******************************************************************************/ 61 #define CORTEX_A57_L2CTLR_EL1 S3_1_C11_C0_2 62 63 #define CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0) 64 #define CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6) 65 66 #define CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2) 67 #define CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2) 68 69 #define CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT (U(1) << 21) 70 71 /******************************************************************************* 72 * L2 Extended Control register specific definitions. 73 ******************************************************************************/ 74 #define CORTEX_A57_L2ECTLR_EL1 S3_1_C11_C0_3 75 76 #define CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT U(0) 77 #define CORTEX_A57_L2ECTLR_RET_CTRL_MASK (U(0x7) << CORTEX_A57_L2ECTLR_RET_CTRL_SHIFT) 78 79 /******************************************************************************* 80 * L2 Memory Error Syndrome register specific definitions. 81 ******************************************************************************/ 82 #define CORTEX_A57_L2MERRSR_EL1 S3_1_C15_C2_3 83 84 #endif /* __CORTEX_A57_H__ */ 85