1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A55_H 8 #define CORTEX_A55_H 9 10 /* Cortex-A55 MIDR for revision 0 */ 11 #define CORTEX_A55_MIDR 0x410fd050 12 13 /******************************************************************************* 14 * CPU Extended Control register specific definitions. 15 ******************************************************************************/ 16 #define CORTEX_A55_CPUPWRCTLR_EL1 S3_0_C15_C2_7 17 #define CORTEX_A55_CPUECTLR_EL1 S3_0_C15_C1_4 18 19 /* Definitions of register field mask in CORTEX_A55_CPUPWRCTLR_EL1 */ 20 #define CORTEX_A55_CORE_PWRDN_EN_MASK 0x1 21 22 #endif /* CORTEX_A55_H */ 23