1c6ac4df6Sjohpow01 /* 2f2bd3528SJohn Powell * Copyright (c) 2022-2025, Arm Limited. All rights reserved. 3c6ac4df6Sjohpow01 * 4c6ac4df6Sjohpow01 * SPDX-License-Identifier: BSD-3-Clause 5c6ac4df6Sjohpow01 */ 6c6ac4df6Sjohpow01 7c6ac4df6Sjohpow01 #ifndef CORTEX_A510_H 8c6ac4df6Sjohpow01 #define CORTEX_A510_H 9c6ac4df6Sjohpow01 10c6ac4df6Sjohpow01 #define CORTEX_A510_MIDR U(0x410FD460) 11c6ac4df6Sjohpow01 12c6ac4df6Sjohpow01 /******************************************************************************* 13c6ac4df6Sjohpow01 * CPU Extended Control register specific definitions 14c6ac4df6Sjohpow01 ******************************************************************************/ 15c6ac4df6Sjohpow01 #define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4 16d48088acSjohpow01 #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19) 17a29cb3c0SJayanth Dodderi Chidanand #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH U(1) 18d48088acSjohpow01 #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1) 19c0959d2cSjohpow01 #define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23) 20c0959d2cSjohpow01 #define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46) 21a67c1b1bSAkram Ahmad #define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2) 22a29cb3c0SJayanth Dodderi Chidanand #define CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT U(38) 23a29cb3c0SJayanth Dodderi Chidanand #define CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH U(3) 24c6ac4df6Sjohpow01 25c6ac4df6Sjohpow01 /******************************************************************************* 26c6ac4df6Sjohpow01 * CPU Power Control register specific definitions 27c6ac4df6Sjohpow01 ******************************************************************************/ 28c6ac4df6Sjohpow01 #define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7 29c6ac4df6Sjohpow01 #define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 30*af1fa796SJohn Powell #define CORTEX_A510_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS 0x70 31*af1fa796SJohn Powell #define CORTEX_A510_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS 0x380 32c6ac4df6Sjohpow01 3383435637Sjohpow01 /******************************************************************************* 3483435637Sjohpow01 * Complex auxiliary control register specific definitions 3583435637Sjohpow01 ******************************************************************************/ 3683435637Sjohpow01 #define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3 37a29cb3c0SJayanth Dodderi Chidanand #define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1) 38a29cb3c0SJayanth Dodderi Chidanand #define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(25) 39a29cb3c0SJayanth Dodderi Chidanand #define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1) 40a29cb3c0SJayanth Dodderi Chidanand #define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE U(3) 41a29cb3c0SJayanth Dodderi Chidanand #define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT U(10) 42a29cb3c0SJayanth Dodderi Chidanand #define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH U(2) 4383435637Sjohpow01 44d5e2512cSjohpow01 /******************************************************************************* 45d5e2512cSjohpow01 * Auxiliary control register specific definitions 46d5e2512cSjohpow01 ******************************************************************************/ 47d5e2512cSjohpow01 #define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0 4811d448c9SAkram Ahmad #define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17) 49afb5d069SAkram Ahmad #define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38) 50a29cb3c0SJayanth Dodderi Chidanand #define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1) 51a29cb3c0SJayanth Dodderi Chidanand #define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(18) 52a29cb3c0SJayanth Dodderi Chidanand #define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1) 53a29cb3c0SJayanth Dodderi Chidanand #define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE U(1) 54a29cb3c0SJayanth Dodderi Chidanand #define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT U(18) 55a29cb3c0SJayanth Dodderi Chidanand #define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH U(1) 56d5e2512cSjohpow01 574592f4eaSJohn Powell /******************************************************************************* 584592f4eaSJohn Powell * Auxiliary control register 2 specific definitions 594592f4eaSJohn Powell ******************************************************************************/ 604592f4eaSJohn Powell #define CORTEX_A510_CPUACTLR2_EL1 S3_0_C15_C1_1 614592f4eaSJohn Powell 624fb7090eSJohn Powell /******************************************************************************* 634fb7090eSJohn Powell * Auxiliary control register 3 specific definitions 644fb7090eSJohn Powell ******************************************************************************/ 654fb7090eSJohn Powell #define CORTEX_A510_CPUACTLR3_EL1 S3_0_C15_C1_2 664fb7090eSJohn Powell 67f2bd3528SJohn Powell #ifndef __ASSEMBLER__ 68f2bd3528SJohn Powell 69f2bd3528SJohn Powell #if ERRATA_A510_2971420 70f2bd3528SJohn Powell long check_erratum_cortex_a510_2971420(long cpu_rev); 71f2bd3528SJohn Powell #endif 72f2bd3528SJohn Powell 73f2bd3528SJohn Powell #endif /* __ASSEMBLER__ */ 74f2bd3528SJohn Powell 75c6ac4df6Sjohpow01 #endif /* CORTEX_A510_H */ 76