1*98c65165SGovindraj Raja /* 2*98c65165SGovindraj Raja * Copyright (c) 2024-2025, Arm Limited. All rights reserved. 3*98c65165SGovindraj Raja * 4*98c65165SGovindraj Raja * SPDX-License-Identifier: BSD-3-Clause 5*98c65165SGovindraj Raja */ 6*98c65165SGovindraj Raja 7*98c65165SGovindraj Raja #ifndef CORTEX_A320_H 8*98c65165SGovindraj Raja #define CORTEX_A320_H 9*98c65165SGovindraj Raja 10*98c65165SGovindraj Raja #define CORTEX_A320_MIDR U(0x410FD8F0) 11*98c65165SGovindraj Raja 12*98c65165SGovindraj Raja /******************************************************************************* 13*98c65165SGovindraj Raja * CPU Extended Control register specific definitions 14*98c65165SGovindraj Raja ******************************************************************************/ 15*98c65165SGovindraj Raja #define CORTEX_A320_CPUECTLR_EL1 S3_0_C15_C1_4 16*98c65165SGovindraj Raja #define CORTEX_A320_CPUECTLR_EL1_EXTLLC_BIT U(0) 17*98c65165SGovindraj Raja 18*98c65165SGovindraj Raja /******************************************************************************* 19*98c65165SGovindraj Raja * CPU Power Control register specific definitions 20*98c65165SGovindraj Raja ******************************************************************************/ 21*98c65165SGovindraj Raja #define CORTEX_A320_CPUPWRCTLR_EL1 S3_0_C15_C2_7 22*98c65165SGovindraj Raja #define CORTEX_A320_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 23*98c65165SGovindraj Raja 24*98c65165SGovindraj Raja #endif /* CORTEX_A320_H */ 25