1*5fc2895cSIcen Zeyada /* 2*5fc2895cSIcen Zeyada * Copyright (c) 2025, Arm Limited. All rights reserved. 3*5fc2895cSIcen Zeyada * 4*5fc2895cSIcen Zeyada * SPDX-License-Identifier: BSD-3-Clause 5*5fc2895cSIcen Zeyada */ 6*5fc2895cSIcen Zeyada 7*5fc2895cSIcen Zeyada #ifndef CANYON_H 8*5fc2895cSIcen Zeyada #define CANYON_H 9*5fc2895cSIcen Zeyada 10*5fc2895cSIcen Zeyada #define CANYON_MIDR U(0x410FD960) 11*5fc2895cSIcen Zeyada 12*5fc2895cSIcen Zeyada /******************************************************************************* 13*5fc2895cSIcen Zeyada * CPU Extended Control register specific definitions 14*5fc2895cSIcen Zeyada ******************************************************************************/ 15*5fc2895cSIcen Zeyada #define CANYON_IMP_CPUECTLR_EL1 S3_0_C15_C1_4 16*5fc2895cSIcen Zeyada 17*5fc2895cSIcen Zeyada /******************************************************************************* 18*5fc2895cSIcen Zeyada * CPU Power Control register specific definitions 19*5fc2895cSIcen Zeyada ******************************************************************************/ 20*5fc2895cSIcen Zeyada #define CANYON_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7 21*5fc2895cSIcen Zeyada #define CANYON_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) 22*5fc2895cSIcen Zeyada 23*5fc2895cSIcen Zeyada #endif /* CANYON_H */ 24*5fc2895cSIcen Zeyada 25