1*656500f9SGovindraj Raja /* 2*656500f9SGovindraj Raja * Copyright (c) 2025, Arm Limited. All rights reserved. 3*656500f9SGovindraj Raja * 4*656500f9SGovindraj Raja * SPDX-License-Identifier: BSD-3-Clause 5*656500f9SGovindraj Raja */ 6*656500f9SGovindraj Raja 7*656500f9SGovindraj Raja #ifndef CADDO_H 8*656500f9SGovindraj Raja #define CADDO_H 9*656500f9SGovindraj Raja 10*656500f9SGovindraj Raja #define CADDO_MIDR U(0x410FDA00) 11*656500f9SGovindraj Raja 12*656500f9SGovindraj Raja /******************************************************************************* 13*656500f9SGovindraj Raja * CPU Extended Control register specific definitions 14*656500f9SGovindraj Raja ******************************************************************************/ 15*656500f9SGovindraj Raja #define CADDO_IMP_CPUECTLR_EL1 S3_0_C15_C1_4 16*656500f9SGovindraj Raja 17*656500f9SGovindraj Raja /******************************************************************************* 18*656500f9SGovindraj Raja * CPU Power Control register specific definitions 19*656500f9SGovindraj Raja ******************************************************************************/ 20*656500f9SGovindraj Raja #define CADDO_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7 21*656500f9SGovindraj Raja #define CADDO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1) 22*656500f9SGovindraj Raja 23*656500f9SGovindraj Raja #endif /* CADDO_H */ 24*656500f9SGovindraj Raja 25