1*7dae0451SMin Yao Ng /* 2*7dae0451SMin Yao Ng * Copyright (c) 2023-2025, Arm Limited. All rights reserved. 3*7dae0451SMin Yao Ng * 4*7dae0451SMin Yao Ng * SPDX-License-Identifier: BSD-3-Clause 5*7dae0451SMin Yao Ng */ 6*7dae0451SMin Yao Ng 7*7dae0451SMin Yao Ng #ifndef C1_PRO_H 8*7dae0451SMin Yao Ng #define C1_PRO_H 9*7dae0451SMin Yao Ng 10*7dae0451SMin Yao Ng #include <lib/utils_def.h> 11*7dae0451SMin Yao Ng 12*7dae0451SMin Yao Ng #define C1_PRO_MIDR U(0x410FD8B0) 13*7dae0451SMin Yao Ng 14*7dae0451SMin Yao Ng /******************************************************************************* 15*7dae0451SMin Yao Ng * CPU Extended Control register specific definitions 16*7dae0451SMin Yao Ng ******************************************************************************/ 17*7dae0451SMin Yao Ng #define C1_PRO_IMP_CPUECTLR_EL1 S3_0_C15_C1_5 18*7dae0451SMin Yao Ng #define C1_PRO_CPUECTLR2_EL1_EXTLLC_BIT U(10) 19*7dae0451SMin Yao Ng 20*7dae0451SMin Yao Ng /******************************************************************************* 21*7dae0451SMin Yao Ng * CPU Power Control register specific definitions 22*7dae0451SMin Yao Ng ******************************************************************************/ 23*7dae0451SMin Yao Ng #define C1_PRO_IMP_CPUPWRCTLR_EL1 S3_0_C15_C2_7 24*7dae0451SMin Yao Ng #define C1_PRO_IMP_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 25*7dae0451SMin Yao Ng 26*7dae0451SMin Yao Ng #endif /* C1_PRO_H */ 27