xref: /rk3399_ARM-atf/include/lib/cpus/aarch32/cpu_macros.S (revision 1a0a3f0622e4b569513304109d9a0d093b71228a)
1e33b78a6SSoby Mathew/*
2e33b78a6SSoby Mathew * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3e33b78a6SSoby Mathew *
4e33b78a6SSoby Mathew * Redistribution and use in source and binary forms, with or without
5e33b78a6SSoby Mathew * modification, are permitted provided that the following conditions are met:
6e33b78a6SSoby Mathew *
7e33b78a6SSoby Mathew * Redistributions of source code must retain the above copyright notice, this
8e33b78a6SSoby Mathew * list of conditions and the following disclaimer.
9e33b78a6SSoby Mathew *
10e33b78a6SSoby Mathew * Redistributions in binary form must reproduce the above copyright notice,
11e33b78a6SSoby Mathew * this list of conditions and the following disclaimer in the documentation
12e33b78a6SSoby Mathew * and/or other materials provided with the distribution.
13e33b78a6SSoby Mathew *
14e33b78a6SSoby Mathew * Neither the name of ARM nor the names of its contributors may be used
15e33b78a6SSoby Mathew * to endorse or promote products derived from this software without specific
16e33b78a6SSoby Mathew * prior written permission.
17e33b78a6SSoby Mathew *
18e33b78a6SSoby Mathew * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19e33b78a6SSoby Mathew * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20e33b78a6SSoby Mathew * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21e33b78a6SSoby Mathew * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22e33b78a6SSoby Mathew * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23e33b78a6SSoby Mathew * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24e33b78a6SSoby Mathew * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25e33b78a6SSoby Mathew * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26e33b78a6SSoby Mathew * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27e33b78a6SSoby Mathew * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28e33b78a6SSoby Mathew * POSSIBILITY OF SUCH DAMAGE.
29e33b78a6SSoby Mathew */
30e33b78a6SSoby Mathew#ifndef __CPU_MACROS_S__
31e33b78a6SSoby Mathew#define __CPU_MACROS_S__
32e33b78a6SSoby Mathew
33e33b78a6SSoby Mathew#include <arch.h>
34e33b78a6SSoby Mathew
35e33b78a6SSoby Mathew#define CPU_IMPL_PN_MASK	(MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
36e33b78a6SSoby Mathew				(MIDR_PN_MASK << MIDR_PN_SHIFT)
37e33b78a6SSoby Mathew
38e33b78a6SSoby Mathew	/*
39e33b78a6SSoby Mathew	 * Define the offsets to the fields in cpu_ops structure.
40e33b78a6SSoby Mathew	 */
41e33b78a6SSoby Mathew	.struct 0
42e33b78a6SSoby MathewCPU_MIDR: /* cpu_ops midr */
43e33b78a6SSoby Mathew	.space  4
44e33b78a6SSoby Mathew/* Reset fn is needed during reset */
45*1a0a3f06SYatharth Kochar#if IMAGE_BL1 || IMAGE_BL32
46e33b78a6SSoby MathewCPU_RESET_FUNC: /* cpu_ops reset_func */
47e33b78a6SSoby Mathew	.space  4
48*1a0a3f06SYatharth Kochar#endif
49*1a0a3f06SYatharth Kochar#if IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
50e33b78a6SSoby MathewCPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */
51e33b78a6SSoby Mathew	.space  4
52e33b78a6SSoby MathewCPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */
53e33b78a6SSoby Mathew	.space  4
54*1a0a3f06SYatharth Kochar#endif
55e33b78a6SSoby MathewCPU_OPS_SIZE = .
56e33b78a6SSoby Mathew
57e33b78a6SSoby Mathew	/*
58e33b78a6SSoby Mathew	 * Convenience macro to declare cpu_ops structure.
59e33b78a6SSoby Mathew	 * Make sure the structure fields are as per the offsets
60e33b78a6SSoby Mathew	 * defined above.
61e33b78a6SSoby Mathew	 */
62e33b78a6SSoby Mathew	.macro declare_cpu_ops _name:req, _midr:req, _noresetfunc = 0
63e33b78a6SSoby Mathew	.section cpu_ops, "a"
64e33b78a6SSoby Mathew	.align 2
65e33b78a6SSoby Mathew	.type cpu_ops_\_name, %object
66e33b78a6SSoby Mathew	.word \_midr
67*1a0a3f06SYatharth Kochar#if IMAGE_BL1 || IMAGE_BL32
68e33b78a6SSoby Mathew	.if \_noresetfunc
69e33b78a6SSoby Mathew	.word 0
70e33b78a6SSoby Mathew	.else
71e33b78a6SSoby Mathew	.word \_name\()_reset_func
72e33b78a6SSoby Mathew	.endif
73*1a0a3f06SYatharth Kochar#endif
74*1a0a3f06SYatharth Kochar#if IMAGE_BL32
75e33b78a6SSoby Mathew	.word \_name\()_core_pwr_dwn
76e33b78a6SSoby Mathew	.word \_name\()_cluster_pwr_dwn
77*1a0a3f06SYatharth Kochar#endif
78e33b78a6SSoby Mathew	.endm
79e33b78a6SSoby Mathew
80e33b78a6SSoby Mathew#endif /* __CPU_MACROS_S__ */
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