1e3148c2bSEtienne Carriere /* 2*4c700c15SGovindraj Raja * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. 3e3148c2bSEtienne Carriere * 4e3148c2bSEtienne Carriere * SPDX-License-Identifier: BSD-3-Clause 5e3148c2bSEtienne Carriere */ 6e3148c2bSEtienne Carriere 7c3cf06f1SAntonio Nino Diaz #ifndef CORTEX_A9_H 8c3cf06f1SAntonio Nino Diaz #define CORTEX_A9_H 9e3148c2bSEtienne Carriere 101a74e4a8SAntonio Nino Diaz #include <lib/utils_def.h> 111a74e4a8SAntonio Nino Diaz 12e3148c2bSEtienne Carriere /******************************************************************************* 13e3148c2bSEtienne Carriere * Cortex-A9 midr with version/revision set to 0 14e3148c2bSEtienne Carriere ******************************************************************************/ 151a74e4a8SAntonio Nino Diaz #define CORTEX_A9_MIDR U(0x410FC090) 16e3148c2bSEtienne Carriere 17e3148c2bSEtienne Carriere /******************************************************************************* 18e3148c2bSEtienne Carriere * CPU Auxiliary Control register specific definitions. 19e3148c2bSEtienne Carriere ******************************************************************************/ 201a74e4a8SAntonio Nino Diaz #define CORTEX_A9_ACTLR_SMP_BIT (U(1) << 6) 211a74e4a8SAntonio Nino Diaz #define CORTEX_A9_ACTLR_FLZW_BIT (U(1) << 3) 22e3148c2bSEtienne Carriere 23e3148c2bSEtienne Carriere /******************************************************************************* 24e3148c2bSEtienne Carriere * CPU Power Control Register 25e3148c2bSEtienne Carriere ******************************************************************************/ 26e3148c2bSEtienne Carriere #define PCR p15, 0, c15, c0, 0 27e3148c2bSEtienne Carriere 28d5dfdeb6SJulius Werner #ifndef __ASSEMBLER__ 29e3148c2bSEtienne Carriere #include <arch_helpers.h> 30e3148c2bSEtienne Carriere DEFINE_COPROCR_RW_FUNCS(pcr, PCR) 31e3148c2bSEtienne Carriere #endif 32e3148c2bSEtienne Carriere 33c3cf06f1SAntonio Nino Diaz #endif /* CORTEX_A9_H */ 34