16ff43c26SEtienne Carriere /* 2*4c700c15SGovindraj Raja * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. 36ff43c26SEtienne Carriere * 46ff43c26SEtienne Carriere * SPDX-License-Identifier: BSD-3-Clause 56ff43c26SEtienne Carriere */ 66ff43c26SEtienne Carriere 7c3cf06f1SAntonio Nino Diaz #ifndef CORTEX_A7_H 8c3cf06f1SAntonio Nino Diaz #define CORTEX_A7_H 96ff43c26SEtienne Carriere 101a74e4a8SAntonio Nino Diaz #include <lib/utils_def.h> 111a74e4a8SAntonio Nino Diaz 126ff43c26SEtienne Carriere /******************************************************************************* 136ff43c26SEtienne Carriere * Cortex-A7 midr with version/revision set to 0 146ff43c26SEtienne Carriere ******************************************************************************/ 151a74e4a8SAntonio Nino Diaz #define CORTEX_A7_MIDR U(0x410FC070) 166ff43c26SEtienne Carriere 176ff43c26SEtienne Carriere /******************************************************************************* 186ff43c26SEtienne Carriere * CPU Auxiliary Control register specific definitions. 196ff43c26SEtienne Carriere ******************************************************************************/ 201a74e4a8SAntonio Nino Diaz #define CORTEX_A7_ACTLR_SMP_BIT (U(1) << 6) 216ff43c26SEtienne Carriere 22c3cf06f1SAntonio Nino Diaz #endif /* CORTEX_A7_H */ 23