1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A53_H 8 #define CORTEX_A53_H 9 10 /* Cortex-A53 midr for revision 0 */ 11 #define CORTEX_A53_MIDR 0x410FD030 12 13 /* Retention timer tick definitions */ 14 #define RETENTION_ENTRY_TICKS_2 0x1 15 #define RETENTION_ENTRY_TICKS_8 0x2 16 #define RETENTION_ENTRY_TICKS_32 0x3 17 #define RETENTION_ENTRY_TICKS_64 0x4 18 #define RETENTION_ENTRY_TICKS_128 0x5 19 #define RETENTION_ENTRY_TICKS_256 0x6 20 #define RETENTION_ENTRY_TICKS_512 0x7 21 22 /******************************************************************************* 23 * CPU Extended Control register specific definitions. 24 ******************************************************************************/ 25 #define CORTEX_A53_ECTLR p15, 1, c15 26 27 #define CORTEX_A53_ECTLR_SMP_BIT (1 << 6) 28 29 #define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT 0 30 #define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT) 31 32 #define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT 3 33 #define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (0x7 << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT) 34 35 /******************************************************************************* 36 * CPU Memory Error Syndrome register specific definitions. 37 ******************************************************************************/ 38 #define CORTEX_A53_MERRSR p15, 2, c15 39 40 /******************************************************************************* 41 * CPU Auxiliary Control register specific definitions. 42 ******************************************************************************/ 43 #define CORTEX_A53_CPUACTLR p15, 0, c15 44 45 #define CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT 44 46 #define CORTEX_A53_CPUACTLR_ENDCCASCI (1 << CORTEX_A53_CPUACTLR_ENDCCASCI_SHIFT) 47 #define CORTEX_A53_CPUACTLR_DTAH (1 << 24) 48 49 /******************************************************************************* 50 * L2 Auxiliary Control register specific definitions. 51 ******************************************************************************/ 52 #define CORTEX_A53_L2ACTLR p15, 1, c15, c0, 0 53 54 #define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (1 << 14) 55 #define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (1 << 3) 56 57 /******************************************************************************* 58 * L2 Extended Control register specific definitions. 59 ******************************************************************************/ 60 #define CORTEX_A53_L2ECTLR p15, 1, c9, c0, 3 61 62 #define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT 0 63 #define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (0x7 << L2ECTLR_RET_CTRL_SHIFT) 64 65 /******************************************************************************* 66 * L2 Memory Error Syndrome register specific definitions. 67 ******************************************************************************/ 68 #define CORTEX_A53_L2MERRSR p15, 3, c15 69 70 #endif /* CORTEX_A53_H */ 71