1d56a8461SEtienne Carriere /* 2*4c700c15SGovindraj Raja * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. 3d56a8461SEtienne Carriere * 4d56a8461SEtienne Carriere * SPDX-License-Identifier: BSD-3-Clause 5d56a8461SEtienne Carriere */ 6d56a8461SEtienne Carriere 7c3cf06f1SAntonio Nino Diaz #ifndef CORTEX_A5_H 8c3cf06f1SAntonio Nino Diaz #define CORTEX_A5_H 9d56a8461SEtienne Carriere 101a74e4a8SAntonio Nino Diaz #include <lib/utils_def.h> 111a74e4a8SAntonio Nino Diaz 12d56a8461SEtienne Carriere /******************************************************************************* 13d56a8461SEtienne Carriere * Cortex-A8 midr with version/revision set to 0 14d56a8461SEtienne Carriere ******************************************************************************/ 151a74e4a8SAntonio Nino Diaz #define CORTEX_A5_MIDR U(0x410FC050) 16d56a8461SEtienne Carriere 17d56a8461SEtienne Carriere /******************************************************************************* 18d56a8461SEtienne Carriere * CPU Auxiliary Control register specific definitions. 19d56a8461SEtienne Carriere ******************************************************************************/ 201a74e4a8SAntonio Nino Diaz #define CORTEX_A5_ACTLR_SMP_BIT (U(1) << 6) 21d56a8461SEtienne Carriere 22c3cf06f1SAntonio Nino Diaz #endif /* CORTEX_A5_H */ 23