103a3042bSYatharth Kochar /* 2*4c700c15SGovindraj Raja * Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved. 303a3042bSYatharth Kochar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 503a3042bSYatharth Kochar */ 603a3042bSYatharth Kochar 7c3cf06f1SAntonio Nino Diaz #ifndef CORTEX_A32_H 8c3cf06f1SAntonio Nino Diaz #define CORTEX_A32_H 903a3042bSYatharth Kochar 101a74e4a8SAntonio Nino Diaz #include <lib/utils_def.h> 111a74e4a8SAntonio Nino Diaz 1203a3042bSYatharth Kochar /* Cortex-A32 Main ID register for revision 0 */ 131a74e4a8SAntonio Nino Diaz #define CORTEX_A32_MIDR U(0x410FD010) 1403a3042bSYatharth Kochar 1503a3042bSYatharth Kochar /******************************************************************************* 1603a3042bSYatharth Kochar * CPU Extended Control register specific definitions. 1703a3042bSYatharth Kochar * CPUECTLR_EL1 is an implementation-specific register. 1803a3042bSYatharth Kochar ******************************************************************************/ 1903a3042bSYatharth Kochar #define CORTEX_A32_CPUECTLR_EL1 p15, 1, c15 201a74e4a8SAntonio Nino Diaz #define CORTEX_A32_CPUECTLR_SMPEN_BIT (ULL(1) << 6) 2103a3042bSYatharth Kochar 22c3cf06f1SAntonio Nino Diaz #endif /* CORTEX_A32_H */ 23