1778e411dSEtienne Carriere /* 2*4c700c15SGovindraj Raja * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. 3778e411dSEtienne Carriere * 4778e411dSEtienne Carriere * SPDX-License-Identifier: BSD-3-Clause 5778e411dSEtienne Carriere */ 6778e411dSEtienne Carriere 7c3cf06f1SAntonio Nino Diaz #ifndef CORTEX_A17_H 8c3cf06f1SAntonio Nino Diaz #define CORTEX_A17_H 9778e411dSEtienne Carriere 101a74e4a8SAntonio Nino Diaz #include <lib/utils_def.h> 111a74e4a8SAntonio Nino Diaz 12778e411dSEtienne Carriere /******************************************************************************* 13778e411dSEtienne Carriere * Cortex-A17 midr with version/revision set to 0 14778e411dSEtienne Carriere ******************************************************************************/ 151a74e4a8SAntonio Nino Diaz #define CORTEX_A17_MIDR U(0x410FC0E0) 16778e411dSEtienne Carriere 17778e411dSEtienne Carriere /******************************************************************************* 18778e411dSEtienne Carriere * CPU Auxiliary Control register specific definitions. 19778e411dSEtienne Carriere ******************************************************************************/ 201a74e4a8SAntonio Nino Diaz #define CORTEX_A17_ACTLR_SMP_BIT (U(1) << 6) 21778e411dSEtienne Carriere 220b64c194SAmbroise Vincent /******************************************************************************* 230b64c194SAmbroise Vincent * Implementation defined register specific definitions. 240b64c194SAmbroise Vincent ******************************************************************************/ 250b64c194SAmbroise Vincent #define CORTEX_A17_IMP_DEF_REG1 p15, 0, c15, c0, 1 260b64c194SAmbroise Vincent 27c3cf06f1SAntonio Nino Diaz #endif /* CORTEX_A17_H */ 28