xref: /rk3399_ARM-atf/include/lib/cpus/aarch32/cortex_a15.h (revision c948f77136c42a92d0bb660543a3600c36dcf7f1)
1 /*
2  * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef CORTEX_A15_H
8 #define CORTEX_A15_H
9 
10 /*******************************************************************************
11  * Cortex-A15 midr with version/revision set to 0
12  ******************************************************************************/
13 #define CORTEX_A15_MIDR			0x410FC0F0
14 
15 /*******************************************************************************
16  * CPU Auxiliary Control register specific definitions.
17  ******************************************************************************/
18 #define CORTEX_A15_ACTLR_INV_BTB_BIT	(1 << 0)
19 #define CORTEX_A15_ACTLR_SMP_BIT	(1 << 6)
20 
21 #endif /* CORTEX_A15_H */
22