11ca8d023SEtienne Carriere /* 2*4c700c15SGovindraj Raja * Copyright (c) 2017-2019, Arm Limited and Contributors. All rights reserved. 31ca8d023SEtienne Carriere * 41ca8d023SEtienne Carriere * SPDX-License-Identifier: BSD-3-Clause 51ca8d023SEtienne Carriere */ 61ca8d023SEtienne Carriere 7c3cf06f1SAntonio Nino Diaz #ifndef CORTEX_A12_H 8c3cf06f1SAntonio Nino Diaz #define CORTEX_A12_H 91ca8d023SEtienne Carriere 101a74e4a8SAntonio Nino Diaz #include <lib/utils_def.h> 111a74e4a8SAntonio Nino Diaz 121ca8d023SEtienne Carriere /******************************************************************************* 131ca8d023SEtienne Carriere * Cortex-A12 midr with version/revision set to 0 141ca8d023SEtienne Carriere ******************************************************************************/ 158785a7cfSHeiko Stuebner #define CORTEX_A12_MIDR U(0x410FC0D0) 161ca8d023SEtienne Carriere 171ca8d023SEtienne Carriere /******************************************************************************* 181ca8d023SEtienne Carriere * CPU Auxiliary Control register specific definitions. 191ca8d023SEtienne Carriere ******************************************************************************/ 201a74e4a8SAntonio Nino Diaz #define CORTEX_A12_ACTLR_SMP_BIT (U(1) << 6) 211ca8d023SEtienne Carriere 22c3cf06f1SAntonio Nino Diaz #endif /* CORTEX_A12_H */ 23