1*1b8898ebSYann Gautier /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 2*1b8898ebSYann Gautier /* 3*1b8898ebSYann Gautier * Copyright (C) STMicroelectronics 2018-2022 - All Rights Reserved 4*1b8898ebSYann Gautier * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics. 5*1b8898ebSYann Gautier */ 6*1b8898ebSYann Gautier 7*1b8898ebSYann Gautier #ifndef _DT_BINDINGS_STM32MP15_RESET_H_ 8*1b8898ebSYann Gautier #define _DT_BINDINGS_STM32MP15_RESET_H_ 9*1b8898ebSYann Gautier 10*1b8898ebSYann Gautier #define MCU_HOLD_BOOT_R 2144 11*1b8898ebSYann Gautier #define LTDC_R 3072 12*1b8898ebSYann Gautier #define DSI_R 3076 13*1b8898ebSYann Gautier #define DDRPERFM_R 3080 14*1b8898ebSYann Gautier #define USBPHY_R 3088 15*1b8898ebSYann Gautier #define SPI6_R 3136 16*1b8898ebSYann Gautier #define I2C4_R 3138 17*1b8898ebSYann Gautier #define I2C6_R 3139 18*1b8898ebSYann Gautier #define USART1_R 3140 19*1b8898ebSYann Gautier #define STGEN_R 3156 20*1b8898ebSYann Gautier #define GPIOZ_R 3200 21*1b8898ebSYann Gautier #define CRYP1_R 3204 22*1b8898ebSYann Gautier #define HASH1_R 3205 23*1b8898ebSYann Gautier #define RNG1_R 3206 24*1b8898ebSYann Gautier #define AXIM_R 3216 25*1b8898ebSYann Gautier #define GPU_R 3269 26*1b8898ebSYann Gautier #define ETHMAC_R 3274 27*1b8898ebSYann Gautier #define FMC_R 3276 28*1b8898ebSYann Gautier #define QSPI_R 3278 29*1b8898ebSYann Gautier #define SDMMC1_R 3280 30*1b8898ebSYann Gautier #define SDMMC2_R 3281 31*1b8898ebSYann Gautier #define CRC1_R 3284 32*1b8898ebSYann Gautier #define USBH_R 3288 33*1b8898ebSYann Gautier #define MDMA_R 3328 34*1b8898ebSYann Gautier #define MCU_R 8225 35*1b8898ebSYann Gautier #define TIM2_R 19456 36*1b8898ebSYann Gautier #define TIM3_R 19457 37*1b8898ebSYann Gautier #define TIM4_R 19458 38*1b8898ebSYann Gautier #define TIM5_R 19459 39*1b8898ebSYann Gautier #define TIM6_R 19460 40*1b8898ebSYann Gautier #define TIM7_R 19461 41*1b8898ebSYann Gautier #define TIM12_R 16462 42*1b8898ebSYann Gautier #define TIM13_R 16463 43*1b8898ebSYann Gautier #define TIM14_R 16464 44*1b8898ebSYann Gautier #define LPTIM1_R 19465 45*1b8898ebSYann Gautier #define SPI2_R 19467 46*1b8898ebSYann Gautier #define SPI3_R 19468 47*1b8898ebSYann Gautier #define USART2_R 19470 48*1b8898ebSYann Gautier #define USART3_R 19471 49*1b8898ebSYann Gautier #define UART4_R 19472 50*1b8898ebSYann Gautier #define UART5_R 19473 51*1b8898ebSYann Gautier #define UART7_R 19474 52*1b8898ebSYann Gautier #define UART8_R 19475 53*1b8898ebSYann Gautier #define I2C1_R 19477 54*1b8898ebSYann Gautier #define I2C2_R 19478 55*1b8898ebSYann Gautier #define I2C3_R 19479 56*1b8898ebSYann Gautier #define I2C5_R 19480 57*1b8898ebSYann Gautier #define SPDIF_R 19482 58*1b8898ebSYann Gautier #define CEC_R 19483 59*1b8898ebSYann Gautier #define DAC12_R 19485 60*1b8898ebSYann Gautier #define MDIO_R 19847 61*1b8898ebSYann Gautier #define TIM1_R 19520 62*1b8898ebSYann Gautier #define TIM8_R 19521 63*1b8898ebSYann Gautier #define TIM15_R 19522 64*1b8898ebSYann Gautier #define TIM16_R 19523 65*1b8898ebSYann Gautier #define TIM17_R 19524 66*1b8898ebSYann Gautier #define SPI1_R 19528 67*1b8898ebSYann Gautier #define SPI4_R 19529 68*1b8898ebSYann Gautier #define SPI5_R 19530 69*1b8898ebSYann Gautier #define USART6_R 19533 70*1b8898ebSYann Gautier #define SAI1_R 19536 71*1b8898ebSYann Gautier #define SAI2_R 19537 72*1b8898ebSYann Gautier #define SAI3_R 19538 73*1b8898ebSYann Gautier #define DFSDM_R 19540 74*1b8898ebSYann Gautier #define FDCAN_R 19544 75*1b8898ebSYann Gautier #define LPTIM2_R 19584 76*1b8898ebSYann Gautier #define LPTIM3_R 19585 77*1b8898ebSYann Gautier #define LPTIM4_R 19586 78*1b8898ebSYann Gautier #define LPTIM5_R 19587 79*1b8898ebSYann Gautier #define SAI4_R 19592 80*1b8898ebSYann Gautier #define SYSCFG_R 19595 81*1b8898ebSYann Gautier #define VREF_R 19597 82*1b8898ebSYann Gautier #define TMPSENS_R 19600 83*1b8898ebSYann Gautier #define PMBCTRL_R 19601 84*1b8898ebSYann Gautier #define DMA1_R 19648 85*1b8898ebSYann Gautier #define DMA2_R 19649 86*1b8898ebSYann Gautier #define DMAMUX_R 19650 87*1b8898ebSYann Gautier #define ADC12_R 19653 88*1b8898ebSYann Gautier #define USBO_R 19656 89*1b8898ebSYann Gautier #define SDMMC3_R 19664 90*1b8898ebSYann Gautier #define CAMITF_R 19712 91*1b8898ebSYann Gautier #define CRYP2_R 19716 92*1b8898ebSYann Gautier #define HASH2_R 19717 93*1b8898ebSYann Gautier #define RNG2_R 19718 94*1b8898ebSYann Gautier #define CRC2_R 19719 95*1b8898ebSYann Gautier #define HSEM_R 19723 96*1b8898ebSYann Gautier #define MBOX_R 19724 97*1b8898ebSYann Gautier #define GPIOA_R 19776 98*1b8898ebSYann Gautier #define GPIOB_R 19777 99*1b8898ebSYann Gautier #define GPIOC_R 19778 100*1b8898ebSYann Gautier #define GPIOD_R 19779 101*1b8898ebSYann Gautier #define GPIOE_R 19780 102*1b8898ebSYann Gautier #define GPIOF_R 19781 103*1b8898ebSYann Gautier #define GPIOG_R 19782 104*1b8898ebSYann Gautier #define GPIOH_R 19783 105*1b8898ebSYann Gautier #define GPIOI_R 19784 106*1b8898ebSYann Gautier #define GPIOJ_R 19785 107*1b8898ebSYann Gautier #define GPIOK_R 19786 108*1b8898ebSYann Gautier 109*1b8898ebSYann Gautier /* SCMI reset domain identifiers */ 110*1b8898ebSYann Gautier #define RST_SCMI0_SPI6 0 111*1b8898ebSYann Gautier #define RST_SCMI0_I2C4 1 112*1b8898ebSYann Gautier #define RST_SCMI0_I2C6 2 113*1b8898ebSYann Gautier #define RST_SCMI0_USART1 3 114*1b8898ebSYann Gautier #define RST_SCMI0_STGEN 4 115*1b8898ebSYann Gautier #define RST_SCMI0_GPIOZ 5 116*1b8898ebSYann Gautier #define RST_SCMI0_CRYP1 6 117*1b8898ebSYann Gautier #define RST_SCMI0_HASH1 7 118*1b8898ebSYann Gautier #define RST_SCMI0_RNG1 8 119*1b8898ebSYann Gautier #define RST_SCMI0_MDMA 9 120*1b8898ebSYann Gautier #define RST_SCMI0_MCU 10 121*1b8898ebSYann Gautier #define RST_SCMI0_MCU_HOLD_BOOT 11 122*1b8898ebSYann Gautier 123*1b8898ebSYann Gautier #endif /* _DT_BINDINGS_STM32MP15_RESET_H_ */ 124