1c948f771SYann Gautier /* 2*f1b6b014SYann Gautier * Copyright (c) 2019-2021, Arm Limited and Contributors. All rights reserved. 30861fcddSAlexei Fedorov * 40861fcddSAlexei Fedorov * SPDX-License-Identifier: MIT 50861fcddSAlexei Fedorov * 6c948f771SYann Gautier * This header provides constants for the ARM GIC. 7c948f771SYann Gautier */ 8c948f771SYann Gautier 9c948f771SYann Gautier #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 10c948f771SYann Gautier #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 11c948f771SYann Gautier 12*f1b6b014SYann Gautier #include <dt-bindings/interrupt-controller/irq.h> 13*f1b6b014SYann Gautier 14c948f771SYann Gautier /* interrupt specifier cell 0 */ 15c948f771SYann Gautier 16c948f771SYann Gautier #define GIC_SPI 0 17c948f771SYann Gautier #define GIC_PPI 1 18c948f771SYann Gautier 19dfa6c540SAlexei Fedorov /* 20dfa6c540SAlexei Fedorov * Interrupt specifier cell 2. 21*f1b6b014SYann Gautier * The flags in irq.h are valid, plus those below. 22dfa6c540SAlexei Fedorov */ 23dfa6c540SAlexei Fedorov #define GIC_CPU_MASK_RAW(x) ((x) << 8) 24*f1b6b014SYann Gautier #define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) 25dfa6c540SAlexei Fedorov 26c948f771SYann Gautier #endif 27