1c948f771SYann Gautier /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 2c948f771SYann Gautier /* 3c948f771SYann Gautier * This header provides constants for the ARM GIC. 4c948f771SYann Gautier */ 5c948f771SYann Gautier 6c948f771SYann Gautier #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 7c948f771SYann Gautier #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 8c948f771SYann Gautier 9c948f771SYann Gautier /* interrupt specifier cell 0 */ 10c948f771SYann Gautier 11c948f771SYann Gautier #define GIC_SPI 0 12c948f771SYann Gautier #define GIC_PPI 1 13c948f771SYann Gautier 14c948f771SYann Gautier #define IRQ_TYPE_NONE 0 15c948f771SYann Gautier #define IRQ_TYPE_EDGE_RISING 1 16c948f771SYann Gautier #define IRQ_TYPE_EDGE_FALLING 2 17c948f771SYann Gautier #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 18c948f771SYann Gautier #define IRQ_TYPE_LEVEL_HIGH 4 19c948f771SYann Gautier #define IRQ_TYPE_LEVEL_LOW 8 20c948f771SYann Gautier 21*dfa6c540SAlexei Fedorov /* 22*dfa6c540SAlexei Fedorov * Interrupt specifier cell 2. 23*dfa6c540SAlexei Fedorov */ 24*dfa6c540SAlexei Fedorov #define GIC_CPU_MASK_RAW(x) ((x) << 8) 25*dfa6c540SAlexei Fedorov 26c948f771SYann Gautier #endif 27