1c948f771SYann Gautier /* 2*0861fcddSAlexei Fedorov * Copyright (c) 2019-2021, ARM Limited and Contributors. All rights reserved. 3*0861fcddSAlexei Fedorov * 4*0861fcddSAlexei Fedorov * SPDX-License-Identifier: MIT 5*0861fcddSAlexei Fedorov * 6c948f771SYann Gautier * This header provides constants for the ARM GIC. 7c948f771SYann Gautier */ 8c948f771SYann Gautier 9c948f771SYann Gautier #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 10c948f771SYann Gautier #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 11c948f771SYann Gautier 12c948f771SYann Gautier /* interrupt specifier cell 0 */ 13c948f771SYann Gautier 14c948f771SYann Gautier #define GIC_SPI 0 15c948f771SYann Gautier #define GIC_PPI 1 16c948f771SYann Gautier 17c948f771SYann Gautier #define IRQ_TYPE_NONE 0 18c948f771SYann Gautier #define IRQ_TYPE_EDGE_RISING 1 19c948f771SYann Gautier #define IRQ_TYPE_EDGE_FALLING 2 20c948f771SYann Gautier #define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) 21c948f771SYann Gautier #define IRQ_TYPE_LEVEL_HIGH 4 22c948f771SYann Gautier #define IRQ_TYPE_LEVEL_LOW 8 23c948f771SYann Gautier 24dfa6c540SAlexei Fedorov /* 25dfa6c540SAlexei Fedorov * Interrupt specifier cell 2. 26dfa6c540SAlexei Fedorov */ 27dfa6c540SAlexei Fedorov #define GIC_CPU_MASK_RAW(x) ((x) << 8) 28dfa6c540SAlexei Fedorov 29c948f771SYann Gautier #endif 30