1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef UFS_H 8 #define UFS_H 9 10 #include <lib/utils_def.h> 11 12 /* register map of UFSHCI */ 13 /* Controller Capabilities */ 14 #define CAP 0x00 15 #define CAP_NUTRS_MASK 0x1F 16 17 /* UFS Version */ 18 #define VER 0x08 19 /* Host Controller Identification - Product ID */ 20 #define HCDDID 0x10 21 /* Host Controller Identification Descriptor - Manufacturer ID */ 22 #define HCPMID 0x14 23 /* Auto-Hibernate Idle Timer */ 24 #define AHIT 0x18 25 /* Interrupt Status */ 26 #define IS 0x20 27 /* Interrupt Enable */ 28 #define IE 0x24 29 /* System Bus Fatal Error Status */ 30 #define UFS_INT_SBFES (1 << 17) 31 /* Host Controller Fatal Error Status */ 32 #define UFS_INT_HCFES (1 << 16) 33 /* UTP Error Status */ 34 #define UFS_INT_UTPES (1 << 12) 35 /* Device Fatal Error Status */ 36 #define UFS_INT_DFES (1 << 11) 37 /* UIC Command Completion Status */ 38 #define UFS_INT_UCCS (1 << 10) 39 /* UTP Task Management Request Completion Status */ 40 #define UFS_INT_UTMRCS (1 << 9) 41 /* UIC Link Startup Status */ 42 #define UFS_INT_ULSS (1 << 8) 43 /* UIC Link Lost Status */ 44 #define UFS_INT_ULLS (1 << 7) 45 /* UIC Hibernate Enter Status */ 46 #define UFS_INT_UHES (1 << 6) 47 /* UIC Hibernate Exit Status */ 48 #define UFS_INT_UHXS (1 << 5) 49 /* UIC Power Mode Status */ 50 #define UFS_INT_UPMS (1 << 4) 51 /* UIC Test Mode Status */ 52 #define UFS_INT_UTMS (1 << 3) 53 /* UIC Error */ 54 #define UFS_INT_UE (1 << 2) 55 /* UIC DME_ENDPOINTRESET Indication */ 56 #define UFS_INT_UDEPRI (1 << 1) 57 /* UTP Transfer Request Completion Status */ 58 #define UFS_INT_UTRCS (1 << 0) 59 60 /* Host Controller Status */ 61 #define HCS 0x30 62 #define HCS_UPMCRS_MASK (7 << 8) 63 #define HCS_PWR_LOCAL (1 << 8) 64 #define HCS_UCRDY (1 << 3) 65 #define HCS_UTMRLRDY (1 << 2) 66 #define HCS_UTRLRDY (1 << 1) 67 #define HCS_DP (1 << 0) 68 69 /* Host Controller Enable */ 70 #define HCE 0x34 71 #define HCE_ENABLE 1 72 #define HCE_DISABLE 0 73 74 /* Host UIC Error Code PHY Adapter Layer */ 75 #define UECPA 0x38 76 /* Host UIC Error Code Data Link Layer */ 77 #define UECDL 0x3C 78 /* Host UIC Error Code Network Layer */ 79 #define UECN 0x40 80 /* Host UIC Error Code Transport Layer */ 81 #define UECT 0x44 82 /* Host UIC Error Code */ 83 #define UECDME 0x48 84 /* UTP Transfer Request Interrupt Aggregation Control Register */ 85 #define UTRIACR 0x4C 86 #define UTRIACR_IAEN (1U << 31) 87 #define UTRIACR_IAPWEN (1 << 24) 88 #define UTRIACR_IASB (1 << 20) 89 #define UTRIACR_CTR (1 << 16) 90 #define UTRIACR_IACTH(x) (((x) & 0x1F) << 8) 91 #define UTRIACR_IATOVAL(x) ((x) & 0xFF) 92 93 /* UTP Transfer Request List Base Address */ 94 #define UTRLBA 0x50 95 /* UTP Transfer Request List Base Address Upper 32-bits */ 96 #define UTRLBAU 0x54 97 /* UTP Transfer Request List Door Bell Register */ 98 #define UTRLDBR 0x58 99 /* UTP Transfer Request List Clear Register */ 100 #define UTRLCLR 0x5C 101 /* UTP Transfer Request List Run Stop Register */ 102 #define UTRLRSR 0x60 103 #define UTMRLBA 0x70 104 #define UTMRLBAU 0x74 105 #define UTMRLDBR 0x78 106 #define UTMRLCLR 0x7C 107 #define UTMRLRSR 0x80 108 /* UIC Command */ 109 #define UICCMD 0x90 110 /* UIC Command Argument 1 */ 111 #define UCMDARG1 0x94 112 /* UIC Command Argument 2 */ 113 #define UCMDARG2 0x98 114 /* UIC Command Argument 3 */ 115 #define UCMDARG3 0x9C 116 117 #define UFS_BLOCK_SHIFT 12 /* 4KB */ 118 #define UFS_BLOCK_SIZE (1 << UFS_BLOCK_SHIFT) 119 #define UFS_BLOCK_MASK (UFS_BLOCK_SIZE - 1) 120 #define UFS_MAX_LUNS 8 121 122 /* UTP Transfer Request Descriptor */ 123 /* Command Type */ 124 #define CT_UFS_STORAGE 1 125 #define CT_SCSI 0 126 127 /* Data Direction */ 128 #define DD_OUT 2 /* Device --> Host */ 129 #define DD_IN 1 /* Host --> Device */ 130 #define DD_NO_DATA_TRANSFER 0 131 132 #define UTP_TRD_SIZE 32 133 134 /* Transaction Type */ 135 #define TRANS_TYPE_HD (1 << 7) /* E2ECRC */ 136 #define TRANS_TYPE_DD (1 << 6) 137 #define TRANS_TYPE_CODE_MASK 0x3F 138 #define QUERY_RESPONSE_UPIU (0x36 << 0) 139 #define READY_TO_TRANSACTION_UPIU (0x31 << 0) 140 #define DATA_IN_UPIU (0x22 << 0) 141 #define RESPONSE_UPIU (0x21 << 0) 142 #define NOP_IN_UPIU (0x20 << 0) 143 #define QUERY_REQUEST_UPIU (0x16 << 0) 144 #define DATA_OUT_UPIU (0x02 << 0) 145 #define CMD_UPIU (0x01 << 0) 146 #define NOP_OUT_UPIU (0x00 << 0) 147 148 #define OCS_SUCCESS 0x0 149 #define OCS_INVALID_FUNC_ATTRIBUTE 0x1 150 #define OCS_MISMATCH_REQUEST_SIZE 0x2 151 #define OCS_MISMATCH_RESPONSE_SIZE 0x3 152 #define OCS_PEER_COMMUNICATION_FAILURE 0x4 153 #define OCS_ABORTED 0x5 154 #define OCS_FATAL_ERROR 0x6 155 #define OCS_MASK 0xF 156 157 /* UIC Command */ 158 #define DME_GET 0x01 159 #define DME_SET 0x02 160 #define DME_PEER_GET 0x03 161 #define DME_PEER_SET 0x04 162 #define DME_POWERON 0x10 163 #define DME_POWEROFF 0x11 164 #define DME_ENABLE 0x12 165 #define DME_RESET 0x14 166 #define DME_ENDPOINTRESET 0x15 167 #define DME_LINKSTARTUP 0x16 168 #define DME_HIBERNATE_ENTER 0x17 169 #define DME_HIBERNATE_EXIT 0x18 170 #define DME_TEST_MODE 0x1A 171 172 #define GEN_SELECTOR_IDX(x) ((x) & 0xFFFF) 173 174 #define CONFIG_RESULT_CODE_MASK 0xFF 175 176 #define CDBCMD_TEST_UNIT_READY 0x00 177 #define CDBCMD_READ_6 0x08 178 #define CDBCMD_WRITE_6 0x0A 179 #define CDBCMD_START_STOP_UNIT 0x1B 180 #define CDBCMD_READ_CAPACITY_10 0x25 181 #define CDBCMD_READ_10 0x28 182 #define CDBCMD_WRITE_10 0x2A 183 #define CDBCMD_READ_16 0x88 184 #define CDBCMD_WRITE_16 0x8A 185 #define CDBCMD_READ_CAPACITY_16 0x9E 186 #define CDBCMD_REPORT_LUNS 0xA0 187 188 #define UPIU_FLAGS_R (1 << 6) 189 #define UPIU_FLAGS_W (1 << 5) 190 #define UPIU_FLAGS_ATTR_MASK (3 << 0) 191 #define UPIU_FLAGS_ATTR_S (0 << 0) /* Simple */ 192 #define UPIU_FLAGS_ATTR_O (1 << 0) /* Ordered */ 193 #define UPIU_FLAGS_ATTR_HQ (2 << 0) /* Head of Queue */ 194 #define UPIU_FLAGS_ATTR_ACA (3 << 0) 195 #define UPIU_FLAGS_O (1 << 6) 196 #define UPIU_FLAGS_U (1 << 5) 197 #define UPIU_FLAGS_D (1 << 4) 198 199 #define QUERY_FUNC_STD_READ 0x01 200 #define QUERY_FUNC_STD_WRITE 0x81 201 202 #define QUERY_NOP 0x00 203 #define QUERY_READ_DESC 0x01 204 #define QUERY_WRITE_DESC 0x02 205 #define QUERY_READ_ATTR 0x03 206 #define QUERY_WRITE_ATTR 0x04 207 #define QUERY_READ_FLAG 0x05 208 #define QUERY_SET_FLAG 0x06 209 #define QUERY_CLEAR_FLAG 0x07 210 #define QUERY_TOGGLE_FLAG 0x08 211 212 #define RW_WITHOUT_CACHE 0x18 213 214 #define DESC_TYPE_DEVICE 0x00 215 #define DESC_TYPE_CONFIGURATION 0x01 216 #define DESC_TYPE_UNIT 0x02 217 #define DESC_TYPE_INTERCONNECT 0x04 218 #define DESC_TYPE_STRING 0x05 219 220 #define DESC_DEVICE_MAX_SIZE 0x1F 221 #define DEVICE_DESC_PARAM_MANF_ID 0x18 222 223 #define ATTR_CUR_PWR_MODE 0x02 /* bCurrentPowerMode */ 224 #define ATTR_ACTIVECC 0x03 /* bActiveICCLevel */ 225 226 #define DEVICE_DESCRIPTOR_LEN 0x40 227 #define UNIT_DESCRIPTOR_LEN 0x23 228 229 #define QUERY_RESP_SUCCESS 0x00 230 #define QUERY_RESP_OPCODE 0xFE 231 #define QUERY_RESP_GENERAL_FAIL 0xFF 232 233 #define SENSE_KEY_NO_SENSE 0x00 234 #define SENSE_KEY_RECOVERED_ERROR 0x01 235 #define SENSE_KEY_NOT_READY 0x02 236 #define SENSE_KEY_MEDIUM_ERROR 0x03 237 #define SENSE_KEY_HARDWARE_ERROR 0x04 238 #define SENSE_KEY_ILLEGAL_REQUEST 0x05 239 #define SENSE_KEY_UNIT_ATTENTION 0x06 240 #define SENSE_KEY_DATA_PROTECT 0x07 241 #define SENSE_KEY_BLANK_CHECK 0x08 242 #define SENSE_KEY_VENDOR_SPECIFIC 0x09 243 #define SENSE_KEY_COPY_ABORTED 0x0A 244 #define SENSE_KEY_ABORTED_COMMAND 0x0B 245 #define SENSE_KEY_VOLUME_OVERFLOW 0x0D 246 #define SENSE_KEY_MISCOMPARE 0x0E 247 248 #define SENSE_DATA_VALID 0x70 249 #define SENSE_DATA_LENGTH 18 250 251 #define READ_CAPACITY_LENGTH 8 252 253 #define FLAG_DEVICE_INIT 0x01 254 255 #define UFS_VENDOR_SKHYNIX U(0x1AD) 256 257 #define MAX_MODEL_LEN 16 258 259 /* maximum number of retries for a general UIC command */ 260 #define UFS_UIC_COMMAND_RETRIES 3 261 262 /* maximum number of retries for reading UFS capacity */ 263 #define UFS_READ_CAPACITY_RETRIES 10 264 265 /* maximum number of link-startup retries */ 266 #define DME_LINKSTARTUP_RETRIES 10 267 268 #define HCE_ENABLE_OUTER_RETRIES 3 269 #define HCE_ENABLE_INNER_RETRIES 50 270 #define HCE_ENABLE_TIMEOUT_US 100 271 #define HCE_DISABLE_TIMEOUT_US 1000 272 273 #define FDEVICEINIT_TIMEOUT_MS 1500 274 275 /** 276 * ufs_dev_desc - ufs device details from the device descriptor 277 * @wmanufacturerid: card details 278 * @model: card model 279 */ 280 struct ufs_dev_desc { 281 uint16_t wmanufacturerid; 282 int8_t model[MAX_MODEL_LEN + 1]; 283 }; 284 285 /* UFS Driver Flags */ 286 #define UFS_FLAGS_SKIPINIT (1 << 0) 287 #define UFS_FLAGS_VENDOR_SKHYNIX (U(1) << 2) 288 289 typedef struct sense_data { 290 uint8_t resp_code : 7; 291 uint8_t valid : 1; 292 uint8_t reserved0; 293 uint8_t sense_key : 4; 294 uint8_t reserved1 : 1; 295 uint8_t ili : 1; 296 uint8_t eom : 1; 297 uint8_t file_mark : 1; 298 uint8_t info[4]; 299 uint8_t asl; 300 uint8_t cmd_spec_len[4]; 301 uint8_t asc; 302 uint8_t ascq; 303 uint8_t fruc; 304 uint8_t sense_key_spec0 : 7; 305 uint8_t sksv : 1; 306 uint8_t sense_key_spec1; 307 uint8_t sense_key_spec2; 308 } sense_data_t; 309 310 /* UTP Transfer Request Descriptor */ 311 typedef struct utrd_header { 312 uint32_t reserved0 : 24; 313 uint32_t i : 1; /* interrupt */ 314 uint32_t dd : 2; /* data direction */ 315 uint32_t reserved1 : 1; 316 uint32_t ct : 4; /* command type */ 317 uint32_t reserved2; 318 uint32_t ocs : 8; /* Overall Command Status */ 319 uint32_t reserved3 : 24; 320 uint32_t reserved4; 321 uint32_t ucdba; /* aligned to 128-byte */ 322 uint32_t ucdbau; /* Upper 32-bits */ 323 uint32_t rul : 16; /* Response UPIU Length */ 324 uint32_t ruo : 16; /* Response UPIU Offset */ 325 uint32_t prdtl : 16; /* PRDT Length */ 326 uint32_t prdto : 16; /* PRDT Offset */ 327 } utrd_header_t; /* 8 words with little endian */ 328 329 /* UTP Task Management Request Descriptor */ 330 typedef struct utp_utmrd { 331 /* 4 words with little endian */ 332 uint32_t reserved0 : 24; 333 uint32_t i : 1; /* interrupt */ 334 uint32_t reserved1 : 7; 335 uint32_t reserved2; 336 uint32_t ocs : 8; /* Overall Command Status */ 337 uint32_t reserved3 : 24; 338 uint32_t reserved4; 339 340 /* followed by 8 words UPIU with big endian */ 341 342 /* followed by 8 words Response UPIU with big endian */ 343 } utp_utmrd_t; 344 345 /* NOP OUT UPIU */ 346 typedef struct nop_out_upiu { 347 uint8_t trans_type; 348 uint8_t flags; 349 uint8_t reserved0; 350 uint8_t task_tag; 351 uint8_t reserved1; 352 uint8_t reserved2; 353 uint8_t reserved3; 354 uint8_t reserved4; 355 uint8_t total_ehs_len; 356 uint8_t reserved5; 357 uint16_t data_segment_len; 358 uint32_t reserved6; 359 uint32_t reserved7; 360 uint32_t reserved8; 361 uint32_t reserved9; 362 uint32_t reserved10; 363 uint32_t e2ecrc; 364 } nop_out_upiu_t; /* 36 bytes with big endian */ 365 366 /* NOP IN UPIU */ 367 typedef struct nop_in_upiu { 368 uint8_t trans_type; 369 uint8_t flags; 370 uint8_t reserved0; 371 uint8_t task_tag; 372 uint8_t reserved1; 373 uint8_t reserved2; 374 uint8_t response; 375 uint8_t reserved3; 376 uint8_t total_ehs_len; 377 uint8_t dev_info; 378 uint16_t data_segment_len; 379 uint32_t reserved4; 380 uint32_t reserved5; 381 uint32_t reserved6; 382 uint32_t reserved7; 383 uint32_t reserved8; 384 uint32_t e2ecrc; 385 } nop_in_upiu_t; /* 36 bytes with big endian */ 386 387 /* Command UPIU */ 388 typedef struct cmd_upiu { 389 uint8_t trans_type; 390 uint8_t flags; 391 uint8_t lun; 392 uint8_t task_tag; 393 uint8_t cmd_set_type; 394 uint8_t reserved0; 395 uint8_t reserved1; 396 uint8_t reserved2; 397 uint8_t total_ehs_len; 398 uint8_t reserved3; 399 uint16_t data_segment_len; 400 uint32_t exp_data_trans_len; 401 /* 402 * A CDB has a fixed length of 16bytes or a variable length 403 * of between 12 and 260 bytes 404 */ 405 uint8_t cdb[16]; /* little endian */ 406 } cmd_upiu_t; /* 32 bytes with big endian except for cdb[] */ 407 408 typedef struct query_desc { 409 uint8_t opcode; 410 uint8_t idn; 411 uint8_t index; 412 uint8_t selector; 413 uint8_t reserved0[2]; 414 uint16_t length; 415 uint32_t reserved2[2]; 416 } query_desc_t; /* 16 bytes with big endian */ 417 418 typedef struct query_flag { 419 uint8_t opcode; 420 uint8_t idn; 421 uint8_t index; 422 uint8_t selector; 423 uint8_t reserved0[7]; 424 uint8_t value; 425 uint32_t reserved8; 426 } query_flag_t; /* 16 bytes with big endian */ 427 428 typedef struct query_attr { 429 uint8_t opcode; 430 uint8_t idn; 431 uint8_t index; 432 uint8_t selector; 433 uint8_t reserved0[4]; 434 uint32_t value; /* little endian */ 435 uint32_t reserved4; 436 } query_attr_t; /* 16 bytes with big endian except for value */ 437 438 /* Query Request UPIU */ 439 typedef struct query_upiu { 440 uint8_t trans_type; 441 uint8_t flags; 442 uint8_t reserved0; 443 uint8_t task_tag; 444 uint8_t reserved1; 445 uint8_t query_func; 446 uint8_t reserved2; 447 uint8_t reserved3; 448 uint8_t total_ehs_len; 449 uint8_t reserved4; 450 uint16_t data_segment_len; 451 /* Transaction Specific Fields */ 452 union { 453 query_desc_t desc; 454 query_flag_t flag; 455 query_attr_t attr; 456 } ts; 457 uint32_t reserved5; 458 } query_upiu_t; /* 32 bytes with big endian */ 459 460 /* Query Response UPIU */ 461 typedef struct query_resp_upiu { 462 uint8_t trans_type; 463 uint8_t flags; 464 uint8_t reserved0; 465 uint8_t task_tag; 466 uint8_t reserved1; 467 uint8_t query_func; 468 uint8_t query_resp; 469 uint8_t reserved2; 470 uint8_t total_ehs_len; 471 uint8_t dev_info; 472 uint16_t data_segment_len; 473 union { 474 query_desc_t desc; 475 query_flag_t flag; 476 query_attr_t attr; 477 } ts; 478 uint32_t reserved3; 479 } query_resp_upiu_t; /* 32 bytes with big endian */ 480 481 /* Response UPIU */ 482 typedef struct resp_upiu { 483 uint8_t trans_type; 484 uint8_t flags; 485 uint8_t lun; 486 uint8_t task_tag; 487 uint8_t cmd_set_type; 488 uint8_t reserved0; 489 uint8_t reserved1; 490 uint8_t status; 491 uint8_t total_ehs_len; 492 uint8_t dev_info; 493 uint16_t data_segment_len; 494 uint32_t res_trans_cnt; /* Residual Transfer Count */ 495 uint32_t reserved2[4]; 496 uint16_t sense_data_len; 497 union { 498 uint8_t sense_data[18]; 499 sense_data_t sense; 500 } sd; 501 } resp_upiu_t; /* 52 bytes with big endian */ 502 503 typedef struct cmd_info { 504 uintptr_t buf; 505 size_t length; 506 int lba; 507 uint8_t op; 508 uint8_t direction; 509 uint8_t lun; 510 } cmd_info_t; 511 512 typedef struct utp_utrd { 513 uintptr_t header; /* utrd_header_t */ 514 uintptr_t upiu; 515 uintptr_t resp_upiu; 516 uintptr_t prdt; 517 size_t size_upiu; 518 size_t size_resp_upiu; 519 size_t size_prdt; 520 int task_tag; 521 } utp_utrd_t; 522 523 /* Physical Region Description Table */ 524 typedef struct prdt { 525 uint32_t dba; /* Data Base Address */ 526 uint32_t dbau; /* Data Base Address Upper 32-bits */ 527 uint32_t reserved0; 528 uint32_t dbc : 18; /* Data Byte Count */ 529 uint32_t reserved1 : 14; 530 } prdt_t; 531 532 typedef struct uic_cmd { 533 uint32_t op; 534 uint32_t arg1; 535 uint32_t arg2; 536 uint32_t arg3; 537 } uic_cmd_t; 538 539 typedef struct ufs_params { 540 uintptr_t reg_base; 541 uintptr_t desc_base; 542 size_t desc_size; 543 unsigned long flags; 544 } ufs_params_t; 545 546 typedef struct ufs_ops { 547 int (*phy_init)(ufs_params_t *params); 548 int (*phy_set_pwr_mode)(ufs_params_t *params); 549 } ufs_ops_t; 550 551 int ufshc_send_uic_cmd(uintptr_t base, uic_cmd_t *cmd); 552 int ufshc_dme_get(unsigned int attr, unsigned int idx, unsigned int *val); 553 int ufshc_dme_set(unsigned int attr, unsigned int idx, unsigned int val); 554 555 unsigned int ufs_read_attr(int idn); 556 void ufs_write_attr(int idn, unsigned int value); 557 unsigned int ufs_read_flag(int idn); 558 void ufs_set_flag(int idn); 559 void ufs_clear_flag(int idn); 560 void ufs_read_desc(int idn, int index, uintptr_t buf, size_t size); 561 void ufs_write_desc(int idn, int index, uintptr_t buf, size_t size); 562 size_t ufs_read_blocks(int lun, int lba, uintptr_t buf, size_t size); 563 size_t ufs_write_blocks(int lun, int lba, const uintptr_t buf, size_t size); 564 int ufs_init(const ufs_ops_t *ops, ufs_params_t *params); 565 566 #endif /* UFS_H */ 567