1*c13b2e32SVarun Wadekar /* 2*c13b2e32SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3*c13b2e32SVarun Wadekar * 4*c13b2e32SVarun Wadekar * Redistribution and use in source and binary forms, with or without 5*c13b2e32SVarun Wadekar * modification, are permitted provided that the following conditions are met: 6*c13b2e32SVarun Wadekar * 7*c13b2e32SVarun Wadekar * Redistributions of source code must retain the above copyright notice, this 8*c13b2e32SVarun Wadekar * list of conditions and the following disclaimer. 9*c13b2e32SVarun Wadekar * 10*c13b2e32SVarun Wadekar * Redistributions in binary form must reproduce the above copyright notice, 11*c13b2e32SVarun Wadekar * this list of conditions and the following disclaimer in the documentation 12*c13b2e32SVarun Wadekar * and/or other materials provided with the distribution. 13*c13b2e32SVarun Wadekar * 14*c13b2e32SVarun Wadekar * Neither the name of ARM nor the names of its contributors may be used 15*c13b2e32SVarun Wadekar * to endorse or promote products derived from this software without specific 16*c13b2e32SVarun Wadekar * prior written permission. 17*c13b2e32SVarun Wadekar * 18*c13b2e32SVarun Wadekar * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19*c13b2e32SVarun Wadekar * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20*c13b2e32SVarun Wadekar * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21*c13b2e32SVarun Wadekar * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22*c13b2e32SVarun Wadekar * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23*c13b2e32SVarun Wadekar * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24*c13b2e32SVarun Wadekar * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25*c13b2e32SVarun Wadekar * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26*c13b2e32SVarun Wadekar * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27*c13b2e32SVarun Wadekar * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28*c13b2e32SVarun Wadekar * POSSIBILITY OF SUCH DAMAGE. 29*c13b2e32SVarun Wadekar */ 30*c13b2e32SVarun Wadekar 31*c13b2e32SVarun Wadekar #ifndef __UART_16550_H__ 32*c13b2e32SVarun Wadekar #define __UART_16550_H__ 33*c13b2e32SVarun Wadekar 34*c13b2e32SVarun Wadekar /* UART16550 Registers */ 35*c13b2e32SVarun Wadekar #define UARTTX 0x0 36*c13b2e32SVarun Wadekar #define UARTRX 0x0 37*c13b2e32SVarun Wadekar #define UARTDLL 0x0 38*c13b2e32SVarun Wadekar #define UARTIER 0x4 39*c13b2e32SVarun Wadekar #define UARTDLLM 0x4 40*c13b2e32SVarun Wadekar #define UARTIIR 0x8 41*c13b2e32SVarun Wadekar #define UARTFCR 0x8 42*c13b2e32SVarun Wadekar #define UARTLCR 0xc 43*c13b2e32SVarun Wadekar #define UARTMCR 0x10 44*c13b2e32SVarun Wadekar #define UARTLSR 0x14 45*c13b2e32SVarun Wadekar #define UARTMSR 0x18 46*c13b2e32SVarun Wadekar #define UARTSPR 0x1c 47*c13b2e32SVarun Wadekar #define UARTCSR 0x20 48*c13b2e32SVarun Wadekar #define UARTRXFIFOCFG 0x24 49*c13b2e32SVarun Wadekar #define UARTMIE 0x28 50*c13b2e32SVarun Wadekar #define UARTVNDR 0x2c 51*c13b2e32SVarun Wadekar #define UARTASR 0x3c 52*c13b2e32SVarun Wadekar 53*c13b2e32SVarun Wadekar /* FIFO Control Register bits */ 54*c13b2e32SVarun Wadekar #define UARTFCR_FIFOMD_16450 (0 << 6) 55*c13b2e32SVarun Wadekar #define UARTFCR_FIFOMD_16550 (1 << 6) 56*c13b2e32SVarun Wadekar #define UARTFCR_RXTRIG_1 (0 << 6) 57*c13b2e32SVarun Wadekar #define UARTFCR_RXTRIG_4 (1 << 6) 58*c13b2e32SVarun Wadekar #define UARTFCR_RXTRIG_8 (2 << 6) 59*c13b2e32SVarun Wadekar #define UARTFCR_RXTRIG_16 (3 << 6) 60*c13b2e32SVarun Wadekar #define UARTFCR_TXTRIG_1 (0 << 4) 61*c13b2e32SVarun Wadekar #define UARTFCR_TXTRIG_4 (1 << 4) 62*c13b2e32SVarun Wadekar #define UARTFCR_TXTRIG_8 (2 << 4) 63*c13b2e32SVarun Wadekar #define UARTFCR_TXTRIG_16 (3 << 4) 64*c13b2e32SVarun Wadekar #define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */ 65*c13b2e32SVarun Wadekar #define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */ 66*c13b2e32SVarun Wadekar #define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */ 67*c13b2e32SVarun Wadekar #define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */ 68*c13b2e32SVarun Wadekar 69*c13b2e32SVarun Wadekar /* Line Control Register bits */ 70*c13b2e32SVarun Wadekar #define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */ 71*c13b2e32SVarun Wadekar #define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */ 72*c13b2e32SVarun Wadekar #define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */ 73*c13b2e32SVarun Wadekar #define UARTLCR_EVEN (1 << 4) /* Even Parity Format */ 74*c13b2e32SVarun Wadekar #define UARTLCR_PAR (1 << 3) /* Parity */ 75*c13b2e32SVarun Wadekar #define UARTLCR_STOP (1 << 2) /* Stop Bit */ 76*c13b2e32SVarun Wadekar #define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */ 77*c13b2e32SVarun Wadekar #define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */ 78*c13b2e32SVarun Wadekar #define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */ 79*c13b2e32SVarun Wadekar #define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */ 80*c13b2e32SVarun Wadekar 81*c13b2e32SVarun Wadekar /* Line Status Register bits */ 82*c13b2e32SVarun Wadekar #define UARTLSR_RXFIFOEMT (1 << 9) /* Rx Fifo Empty */ 83*c13b2e32SVarun Wadekar #define UARTLSR_TXFIFOFULL (1 << 8) /* Tx Fifo Full */ 84*c13b2e32SVarun Wadekar #define UARTLSR_RXFIFOERR (1 << 7) /* Rx Fifo Error */ 85*c13b2e32SVarun Wadekar #define UARTLSR_TEMT (1 << 6) /* Tx Shift Register Empty */ 86*c13b2e32SVarun Wadekar #define UARTLSR_THRE (1 << 5) /* Tx Holding Register Empty */ 87*c13b2e32SVarun Wadekar #define UARTLSR_BRK (1 << 4) /* Break Condition Detected */ 88*c13b2e32SVarun Wadekar #define UARTLSR_FERR (1 << 3) /* Framing Error */ 89*c13b2e32SVarun Wadekar #define UARTLSR_PERR (1 << 3) /* Parity Error */ 90*c13b2e32SVarun Wadekar #define UARTLSR_OVRF (1 << 2) /* Rx Overrun Error */ 91*c13b2e32SVarun Wadekar #define UARTLSR_RDR (1 << 2) /* Rx Data Ready */ 92*c13b2e32SVarun Wadekar 93*c13b2e32SVarun Wadekar #endif /* __UART_16550_H__ */ 94