1c13b2e32SVarun Wadekar /* 2c13b2e32SVarun Wadekar * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3c13b2e32SVarun Wadekar * 4*82cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5c13b2e32SVarun Wadekar */ 6c13b2e32SVarun Wadekar 7c13b2e32SVarun Wadekar #ifndef __UART_16550_H__ 8c13b2e32SVarun Wadekar #define __UART_16550_H__ 9c13b2e32SVarun Wadekar 10c13b2e32SVarun Wadekar /* UART16550 Registers */ 11c13b2e32SVarun Wadekar #define UARTTX 0x0 12c13b2e32SVarun Wadekar #define UARTRX 0x0 13c13b2e32SVarun Wadekar #define UARTDLL 0x0 14c13b2e32SVarun Wadekar #define UARTIER 0x4 15c13b2e32SVarun Wadekar #define UARTDLLM 0x4 16c13b2e32SVarun Wadekar #define UARTIIR 0x8 17c13b2e32SVarun Wadekar #define UARTFCR 0x8 18c13b2e32SVarun Wadekar #define UARTLCR 0xc 19c13b2e32SVarun Wadekar #define UARTMCR 0x10 20c13b2e32SVarun Wadekar #define UARTLSR 0x14 21c13b2e32SVarun Wadekar #define UARTMSR 0x18 22c13b2e32SVarun Wadekar #define UARTSPR 0x1c 23c13b2e32SVarun Wadekar #define UARTCSR 0x20 24c13b2e32SVarun Wadekar #define UARTRXFIFOCFG 0x24 25c13b2e32SVarun Wadekar #define UARTMIE 0x28 26c13b2e32SVarun Wadekar #define UARTVNDR 0x2c 27c13b2e32SVarun Wadekar #define UARTASR 0x3c 28c13b2e32SVarun Wadekar 29c13b2e32SVarun Wadekar /* FIFO Control Register bits */ 30c13b2e32SVarun Wadekar #define UARTFCR_FIFOMD_16450 (0 << 6) 31c13b2e32SVarun Wadekar #define UARTFCR_FIFOMD_16550 (1 << 6) 32c13b2e32SVarun Wadekar #define UARTFCR_RXTRIG_1 (0 << 6) 33c13b2e32SVarun Wadekar #define UARTFCR_RXTRIG_4 (1 << 6) 34c13b2e32SVarun Wadekar #define UARTFCR_RXTRIG_8 (2 << 6) 35c13b2e32SVarun Wadekar #define UARTFCR_RXTRIG_16 (3 << 6) 36c13b2e32SVarun Wadekar #define UARTFCR_TXTRIG_1 (0 << 4) 37c13b2e32SVarun Wadekar #define UARTFCR_TXTRIG_4 (1 << 4) 38c13b2e32SVarun Wadekar #define UARTFCR_TXTRIG_8 (2 << 4) 39c13b2e32SVarun Wadekar #define UARTFCR_TXTRIG_16 (3 << 4) 40c13b2e32SVarun Wadekar #define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */ 41c13b2e32SVarun Wadekar #define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */ 42c13b2e32SVarun Wadekar #define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */ 43c13b2e32SVarun Wadekar #define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */ 44c13b2e32SVarun Wadekar 45c13b2e32SVarun Wadekar /* Line Control Register bits */ 46c13b2e32SVarun Wadekar #define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */ 47c13b2e32SVarun Wadekar #define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */ 48c13b2e32SVarun Wadekar #define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */ 49c13b2e32SVarun Wadekar #define UARTLCR_EVEN (1 << 4) /* Even Parity Format */ 50c13b2e32SVarun Wadekar #define UARTLCR_PAR (1 << 3) /* Parity */ 51c13b2e32SVarun Wadekar #define UARTLCR_STOP (1 << 2) /* Stop Bit */ 52c13b2e32SVarun Wadekar #define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */ 53c13b2e32SVarun Wadekar #define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */ 54c13b2e32SVarun Wadekar #define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */ 55c13b2e32SVarun Wadekar #define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */ 56c13b2e32SVarun Wadekar 57c13b2e32SVarun Wadekar /* Line Status Register bits */ 58c13b2e32SVarun Wadekar #define UARTLSR_RXFIFOEMT (1 << 9) /* Rx Fifo Empty */ 59c13b2e32SVarun Wadekar #define UARTLSR_TXFIFOFULL (1 << 8) /* Tx Fifo Full */ 60c13b2e32SVarun Wadekar #define UARTLSR_RXFIFOERR (1 << 7) /* Rx Fifo Error */ 61c13b2e32SVarun Wadekar #define UARTLSR_TEMT (1 << 6) /* Tx Shift Register Empty */ 62c13b2e32SVarun Wadekar #define UARTLSR_THRE (1 << 5) /* Tx Holding Register Empty */ 63c13b2e32SVarun Wadekar #define UARTLSR_BRK (1 << 4) /* Break Condition Detected */ 64c13b2e32SVarun Wadekar #define UARTLSR_FERR (1 << 3) /* Framing Error */ 65c13b2e32SVarun Wadekar #define UARTLSR_PERR (1 << 3) /* Parity Error */ 66c13b2e32SVarun Wadekar #define UARTLSR_OVRF (1 << 2) /* Rx Overrun Error */ 67861ac52aSNishanth Menon #define UARTLSR_RDR_BIT (0) /* Rx Data Ready Bit */ 68861ac52aSNishanth Menon #define UARTLSR_RDR (1 << UARTLSR_RDR_BIT) /* Rx Data Ready */ 69c13b2e32SVarun Wadekar 70c13b2e32SVarun Wadekar #endif /* __UART_16550_H__ */ 71