1c13b2e32SVarun Wadekar /* 293c78ed2SAntonio Nino Diaz * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3c13b2e32SVarun Wadekar * 482cb2c1aSdp-arm * SPDX-License-Identifier: BSD-3-Clause 5c13b2e32SVarun Wadekar */ 6c13b2e32SVarun Wadekar 7c3cf06f1SAntonio Nino Diaz #ifndef UART_16550_H 8c3cf06f1SAntonio Nino Diaz #define UART_16550_H 9c13b2e32SVarun Wadekar 10*09d40e0eSAntonio Nino Diaz #include <drivers/console.h> 1136c42ca1SJulius Werner 12c13b2e32SVarun Wadekar /* UART16550 Registers */ 13c13b2e32SVarun Wadekar #define UARTTX 0x0 14c13b2e32SVarun Wadekar #define UARTRX 0x0 15c13b2e32SVarun Wadekar #define UARTDLL 0x0 16c13b2e32SVarun Wadekar #define UARTIER 0x4 17c13b2e32SVarun Wadekar #define UARTDLLM 0x4 18c13b2e32SVarun Wadekar #define UARTIIR 0x8 19c13b2e32SVarun Wadekar #define UARTFCR 0x8 20c13b2e32SVarun Wadekar #define UARTLCR 0xc 21c13b2e32SVarun Wadekar #define UARTMCR 0x10 22c13b2e32SVarun Wadekar #define UARTLSR 0x14 23c13b2e32SVarun Wadekar #define UARTMSR 0x18 24c13b2e32SVarun Wadekar #define UARTSPR 0x1c 25c13b2e32SVarun Wadekar #define UARTCSR 0x20 26529b541eSBenjamin Fair /* Some instances have MDR1 defined as well */ 27529b541eSBenjamin Fair #define UARTMDR1 0x20 28c13b2e32SVarun Wadekar #define UARTRXFIFOCFG 0x24 29c13b2e32SVarun Wadekar #define UARTMIE 0x28 30c13b2e32SVarun Wadekar #define UARTVNDR 0x2c 31c13b2e32SVarun Wadekar #define UARTASR 0x3c 32c13b2e32SVarun Wadekar 33c13b2e32SVarun Wadekar /* FIFO Control Register bits */ 34c13b2e32SVarun Wadekar #define UARTFCR_FIFOMD_16450 (0 << 6) 35c13b2e32SVarun Wadekar #define UARTFCR_FIFOMD_16550 (1 << 6) 36c13b2e32SVarun Wadekar #define UARTFCR_RXTRIG_1 (0 << 6) 37c13b2e32SVarun Wadekar #define UARTFCR_RXTRIG_4 (1 << 6) 38c13b2e32SVarun Wadekar #define UARTFCR_RXTRIG_8 (2 << 6) 39c13b2e32SVarun Wadekar #define UARTFCR_RXTRIG_16 (3 << 6) 40c13b2e32SVarun Wadekar #define UARTFCR_TXTRIG_1 (0 << 4) 41c13b2e32SVarun Wadekar #define UARTFCR_TXTRIG_4 (1 << 4) 42c13b2e32SVarun Wadekar #define UARTFCR_TXTRIG_8 (2 << 4) 43c13b2e32SVarun Wadekar #define UARTFCR_TXTRIG_16 (3 << 4) 44c13b2e32SVarun Wadekar #define UARTFCR_DMAEN (1 << 3) /* Enable DMA mode */ 45c13b2e32SVarun Wadekar #define UARTFCR_TXCLR (1 << 2) /* Clear contents of Tx FIFO */ 46c13b2e32SVarun Wadekar #define UARTFCR_RXCLR (1 << 1) /* Clear contents of Rx FIFO */ 47c13b2e32SVarun Wadekar #define UARTFCR_FIFOEN (1 << 0) /* Enable the Tx/Rx FIFO */ 48c13b2e32SVarun Wadekar 49c13b2e32SVarun Wadekar /* Line Control Register bits */ 50c13b2e32SVarun Wadekar #define UARTLCR_DLAB (1 << 7) /* Divisor Latch Access */ 51c13b2e32SVarun Wadekar #define UARTLCR_SETB (1 << 6) /* Set BREAK Condition */ 52c13b2e32SVarun Wadekar #define UARTLCR_SETP (1 << 5) /* Set Parity to LCR[4] */ 53c13b2e32SVarun Wadekar #define UARTLCR_EVEN (1 << 4) /* Even Parity Format */ 54c13b2e32SVarun Wadekar #define UARTLCR_PAR (1 << 3) /* Parity */ 55c13b2e32SVarun Wadekar #define UARTLCR_STOP (1 << 2) /* Stop Bit */ 56c13b2e32SVarun Wadekar #define UARTLCR_WORDSZ_5 0 /* Word Length of 5 */ 57c13b2e32SVarun Wadekar #define UARTLCR_WORDSZ_6 1 /* Word Length of 6 */ 58c13b2e32SVarun Wadekar #define UARTLCR_WORDSZ_7 2 /* Word Length of 7 */ 59c13b2e32SVarun Wadekar #define UARTLCR_WORDSZ_8 3 /* Word Length of 8 */ 60c13b2e32SVarun Wadekar 61c13b2e32SVarun Wadekar /* Line Status Register bits */ 62c13b2e32SVarun Wadekar #define UARTLSR_RXFIFOEMT (1 << 9) /* Rx Fifo Empty */ 63c13b2e32SVarun Wadekar #define UARTLSR_TXFIFOFULL (1 << 8) /* Tx Fifo Full */ 64c13b2e32SVarun Wadekar #define UARTLSR_RXFIFOERR (1 << 7) /* Rx Fifo Error */ 65c13b2e32SVarun Wadekar #define UARTLSR_TEMT (1 << 6) /* Tx Shift Register Empty */ 66c13b2e32SVarun Wadekar #define UARTLSR_THRE (1 << 5) /* Tx Holding Register Empty */ 67c13b2e32SVarun Wadekar #define UARTLSR_BRK (1 << 4) /* Break Condition Detected */ 68c13b2e32SVarun Wadekar #define UARTLSR_FERR (1 << 3) /* Framing Error */ 69c13b2e32SVarun Wadekar #define UARTLSR_PERR (1 << 3) /* Parity Error */ 70c13b2e32SVarun Wadekar #define UARTLSR_OVRF (1 << 2) /* Rx Overrun Error */ 71861ac52aSNishanth Menon #define UARTLSR_RDR_BIT (0) /* Rx Data Ready Bit */ 72861ac52aSNishanth Menon #define UARTLSR_RDR (1 << UARTLSR_RDR_BIT) /* Rx Data Ready */ 73c13b2e32SVarun Wadekar 7436c42ca1SJulius Werner #define CONSOLE_T_16550_BASE CONSOLE_T_DRVDATA 7536c42ca1SJulius Werner 7636c42ca1SJulius Werner #ifndef __ASSEMBLY__ 7736c42ca1SJulius Werner 7893c78ed2SAntonio Nino Diaz #include <stdint.h> 7936c42ca1SJulius Werner 8036c42ca1SJulius Werner typedef struct { 8136c42ca1SJulius Werner console_t console; 8236c42ca1SJulius Werner uintptr_t base; 8336c42ca1SJulius Werner } console_16550_t; 8436c42ca1SJulius Werner 8536c42ca1SJulius Werner /* 8636c42ca1SJulius Werner * Initialize a new 16550 console instance and register it with the console 8736c42ca1SJulius Werner * framework. The |console| pointer must point to storage that will be valid 8836c42ca1SJulius Werner * for the lifetime of the console, such as a global or static local variable. 8936c42ca1SJulius Werner * Its contents will be reinitialized from scratch. 9036c42ca1SJulius Werner */ 9136c42ca1SJulius Werner int console_16550_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud, 9236c42ca1SJulius Werner console_16550_t *console); 9336c42ca1SJulius Werner 9436c42ca1SJulius Werner #endif /*__ASSEMBLY__*/ 9536c42ca1SJulius Werner 96c3cf06f1SAntonio Nino Diaz #endif /* UART_16550_H */ 97