1 /* 2 * Copyright (c) 2015-2025, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __USB_DWC3_H 8 #define __USB_DWC3_H 9 10 #include <drivers/usb_device.h> 11 #include <platform_def.h> 12 13 /* define value use in register */ 14 15 #define USB3_HS_MAX_PACKET_SIZE 512U 16 #define USB3_FS_MAX_PACKET_SIZE 64U 17 #ifdef USE_USB_FS 18 #define USB3_MAX_PACKET_SIZE USB3_FS_MAX_PACKET_SIZE 19 #else 20 #define USB3_MAX_PACKET_SIZE USB3_HS_MAX_PACKET_SIZE 21 #endif 22 #define USB_SETUP_PACKET_SIZE 12U 23 24 /* USB_DWC3_EPTypeDef->trb_flag */ 25 #define USB_DWC3_TRBCTL_NORMAL 1 26 #define USB_DWC3_TRBCTL_CONTROL_SETUP 2 27 #define USB_DWC3_TRBCTL_CONTROL_STATUS2 3 28 #define USB_DWC3_TRBCTL_CONTROL_STATUS3 4 29 #define USB_DWC3_TRBCTL_CONTROL_DATA 5 30 #define USB_DWC3_TRBCTL_ISOCHRONOUS_FIRST 6 31 #define USB_DWC3_TRBCTL_ISOCHRONOUS 7 32 #define USB_DWC3_TRBCTL_LINK_TRB 8 33 #define USB_DWC3_TRBCTL_MASK 0x3fUL 34 35 /* USB_DWC3_EPTypeDef->flags */ 36 #define USB_DWC3_EP_REQ_QUEUED BIT(0) 37 #define USB_DWC3_EP_ISOC_START_PENDING BIT(1) 38 #define USB_DWC3_EP_ISOC_STARTED BIT(2) 39 40 /* 41 * DWC3 Specific Configurable macros 42 */ 43 #define USB_DWC3_INT_INUSE 1U 44 #define USB_DWC3_EVENT_BUFFER_SIZE 2048U 45 #define USB_DWC3_NUM_IN_EP USBD_EP_NB 46 #define USB_DWC3_NUM_OUT_EP USBD_EP_NB 47 48 typedef struct { 49 uint32_t dcfg; /* @ offset 0x0 */ 50 uint32_t dctl; /* @ offset 0x4 */ 51 uint32_t devten; /* @ offset 0x8 */ 52 uint32_t dsts; /* @ offset 0xc */ 53 uint32_t dgcmdpar; /* @ offset 0x10 */ 54 uint32_t dgcmd; /* @ offset 0x14 */ 55 uint32_t reserved_18[2]; /* Reserved @ offset 0x18 */ 56 uint32_t dalepena; /* @ offset 0x20 */ 57 uint32_t reserved_24; /* @ offset 0x24 */ 58 uint32_t reserved_28[54]; /* Reserved @ offset 0x28 */ 59 uint32_t depcmdpar2; /* @ offset 0x100 */ 60 uint32_t depcmdpar1; /* @ offset 0x104 */ 61 uint32_t depcmdpar0; /* @ offset 0x108 */ 62 uint32_t depcmd; /* @ offset 0x10c */ 63 uint32_t reserved_110[124];/* Reserved @ offset 0x110 */ 64 uint32_t dev_imod; /* @ offset 0x300 */ 65 uint32_t reserved_304[0xfc / 4]; /* Reserved @ offset 0x304 */ 66 } usb_dwc3_device_t; 67 68 typedef struct { 69 uint32_t gsbuscfg0; /* @ offset 0x0 */ 70 uint32_t gsbuscfg1; /* @ offset 0x4 */ 71 uint32_t gtxthrcfg; /* @ offset 0x8 */ 72 uint32_t grxthrcfg; /* @ offset 0xc */ 73 uint32_t gctl; /* @ offset 0x10 */ 74 uint32_t gpmsts; /* @ offset 0x14 */ 75 uint32_t gsts; /* @ offset 0x18 */ 76 uint32_t guctl1; /* @ offset 0x1c */ 77 uint32_t gsnpsid; /* @ offset 0x20 */ 78 uint32_t ggpio; /* @ offset 0x24 */ 79 uint32_t guid; /* @ offset 0x28 */ 80 uint32_t guctl; /* @ offset 0x2c */ 81 uint32_t gbuserraddrlo; /* @ offset 0x30 */ 82 uint32_t gbuserraddrhi; /* @ offset 0x34 */ 83 uint32_t gprtbimaplo; /* @ offset 0x38 */ 84 uint32_t gprtbimaphi; /* @ offset 0x3c */ 85 uint32_t ghwparams0; /* @ offset 0x40 */ 86 uint32_t ghwparams1; /* @ offset 0x44 */ 87 uint32_t ghwparams2; /* @ offset 0x48 */ 88 uint32_t ghwparams3; /* @ offset 0x4c */ 89 uint32_t ghwparams4; /* @ offset 0x50 */ 90 uint32_t ghwparams5; /* @ offset 0x54 */ 91 uint32_t ghwparams6; /* @ offset 0x58 */ 92 uint32_t ghwparams7; /* @ offset 0x5c */ 93 uint32_t gdbgfifospace; /* @ offset 0x60 */ 94 uint32_t gdbgltssm; /* @ offset 0x64 */ 95 uint32_t gdbglnmcc; /* @ offset 0x68 */ 96 uint32_t gdbgbmu; /* @ offset 0x6c */ 97 uint32_t gdbglspmux_hst; /* @ offset 0x70 */ 98 uint32_t gdbglsp; /* @ offset 0x74 */ 99 uint32_t gdbgepinfo0; /* @ offset 0x78 */ 100 uint32_t gdbgepinfo1; /* @ offset 0x7c */ 101 uint32_t gprtbimap_hslo; /* @ offset 0x80 */ 102 uint32_t gprtbimap_hshi; /* @ offset 0x84 */ 103 uint32_t gprtbimap_fslo; /* @ offset 0x88 */ 104 uint32_t gprtbimap_fshi; /* @ offset 0x8c */ 105 uint32_t reserved_90; /* Reserved @ offset 0x90 */ 106 uint32_t reserved_94; /* @ offset 0x94 */ 107 uint32_t reserved_98; /* @ offset 0x98 */ 108 uint32_t guctl2; /* @ offset 0x9c */ 109 uint32_t reserved_A0[24]; /* Reserved @ offset 0xa0 */ 110 uint32_t gusb2phycfg; /* @ offset 0x100 */ 111 uint32_t reserved_104[15]; /* Reserved @ offset 0x104 */ 112 uint32_t gusb2i2cctl; /* @ offset 0x140 */ 113 uint32_t reserved_144[15]; /* Reserved @ offset 0x144 */ 114 uint32_t gusb2phyacc_ulpi; /* @ offset 0x180 */ 115 uint32_t reserved_184[15]; /* Reserved @ offset 0x184 */ 116 uint32_t gusb3pipectl; /* @ offset 0x1c0 */ 117 uint32_t reserved_1c4[15]; /* Reserved @ offset 0x1c4 */ 118 uint32_t gtxfifosiz0; /* @ offset 0x200 */ 119 uint32_t gtxfifosiz1; /* @ offset 0x204 */ 120 uint32_t gtxfifosiz2; /* @ offset 0x208 */ 121 uint32_t gtxfifosiz3; /* @ offset 0x20c */ 122 uint32_t gtxfifosiz4; /* @ offset 0x210 */ 123 uint32_t gtxfifosiz5; /* @ offset 0x214 */ 124 uint32_t gtxfifosiz6; /* @ offset 0x218 */ 125 uint32_t gtxfifosiz7; /* @ offset 0x21c */ 126 uint32_t gtxfifosiz8; /* @ offset 0x220 */ 127 uint32_t gtxfifosiz9; /* @ offset 0x224 */ 128 uint32_t gtxfifosiz10; /* @ offset 0x228 */ 129 uint32_t gtxfifosiz11; /* @ offset 0x22c */ 130 uint32_t reserved_230[20]; /* Reserved @ offset 0x230 */ 131 uint32_t grxfifosiz0; /* @ offset 0x280 */ 132 uint32_t grxfifosiz1; /* @ offset 0x284 */ 133 uint32_t grxfifosiz2; /* @ offset 0x288 */ 134 uint32_t reserved_28c[29]; /* Reserved @ offset 0x28c */ 135 uint32_t gevntadrlo; /* @ offset 0x300 */ 136 uint32_t gevntadrhi; /* @ offset 0x304 */ 137 uint32_t gevntsiz; /* @ offset 0x308 */ 138 uint32_t gevntcount; /* @ offset 0x30c */ 139 uint32_t reserved_310[124]; /* Reserved @ offset 0x310 */ 140 uint32_t ghwparams8; /* @ offset 0x500 */ 141 uint32_t reserved_504[3]; /* Reserved @ offset 0x504 */ 142 uint32_t gtxfifopridev; /* @ offset 0x510 */ 143 uint32_t reserved_514; /* Reserved @ offset 0x514 */ 144 uint32_t gtxfifoprihst; /* @ offset 0x518 */ 145 uint32_t grxfifoprihst; /* @ offset 0x51c */ 146 uint32_t reserved_520; /* Reserved @ offset 0x520 */ 147 uint32_t gdmahlratio; /* @ offset 0x524 */ 148 uint32_t reserved_528[2]; /* Reserved @ offset 0x528 */ 149 uint32_t gfladj; /* @ offset 0x530 */ 150 uint32_t reserved_534[0xcc / 4]; /* Reserved @ offset 0x534 */ 151 } usb_dwc3_global_t; 152 153 typedef struct { 154 uint32_t bpl; /* Buffer Pointer Low Address */ 155 uint32_t bph; /* Buffer Pointer High Address */ 156 uint32_t size; /* Buffer Size */ 157 uint32_t ctrl; /* Control and Status field */ 158 } __packed usb_dwc3_trb_t __aligned(16); 159 160 #define CACHED_MEMORY 161 #define CACHE_LINE_SIZE CACHE_WRITEBACK_GRANULE 162 163 typedef struct { 164 bool is_stall; /* Endpoint stall condition */ 165 166 volatile usb_dwc3_trb_t *trb_addr; /* Trb descriptor coherent address */ 167 uintptr_t trb_dma_addr; /* 32 bits aligned trb bus address */ 168 uint8_t trb_flag; /* TRB Control Flag */ 169 uint8_t flags; /* Endpoint state flags condition */ 170 uint8_t phy_epnum; /* physical EP number 0 - 31 */ 171 uint8_t intr_num; /* Interrupt number to get events for this EP */ 172 /* to be used for receiving packet < EP-Max-Packet-Size */ 173 uint8_t *bounce_buf; 174 /* Transmission FIFO number. Number between Min_Data = 1 and Max_Data = 15 */ 175 uint8_t tx_fifo_num; 176 uint8_t resc_idx; /* Resource index */ 177 uintptr_t dma_addr; /* 32 bits aligned transfer buffer address */ 178 /* Pointer to destination buffer, used for receive case, where bounce_buf is used */ 179 uint8_t *xfer_dest_buff; 180 /* length of destination buffer, used for receive case, where bounce_buf is used */ 181 uint32_t xfer_dest_len; 182 } usb_dwc3_endpoint_t; 183 184 typedef struct { 185 uint8_t bounce_buf[USB3_MAX_PACKET_SIZE]; /* Event Buffer area */ 186 } usb_dwc3_endpoint_bouncebuf_t __aligned(CACHE_LINE_SIZE); 187 188 /* Aligned to make EvtBuffer start address evtbuffer-size aligned */ 189 typedef struct { 190 uint8_t EvtBufferArea[USB_DWC3_EVENT_BUFFER_SIZE]; /* Event Buffer area */ 191 } PCD_intbufferareadef __aligned(USB_DWC3_EVENT_BUFFER_SIZE); 192 193 typedef struct { 194 /* shield needed for the cache line (8 words) intersection with other members of structure, 195 * only when USB_DWC3_EVENT_BUFFER_SIZE is non-cache_line aligned 196 */ 197 198 uint8_t *evtbuffer_addr[USB_DWC3_INT_INUSE]; /* Event Buffer coherent addr */ 199 uintptr_t evtbuffer_dma_addr[USB_DWC3_INT_INUSE]; /* Event Buffer dma addr */ 200 uint32_t evtbufferpos[USB_DWC3_INT_INUSE]; /*!< Read Position inside the Event Buffer */ 201 } PCD_intbuffersdef; 202 203 typedef enum { 204 HAL_PCD_STATE_RESET = 0x00U, 205 HAL_PCD_STATE_READY = 0x01U, 206 HAL_PCD_STATE_ERROR = 0x02U, 207 HAL_PCD_STATE_BUSY = 0x03U, 208 HAL_PCD_STATE_TIMEOUT = 0x04U 209 } usb_dwc3_state_t; 210 211 typedef enum { 212 HAL_PCD_EP0_SETUP_COMPLETED = 0x00U, 213 HAL_PCD_EP0_SETUP_QUEUED = 0x01U 214 } usb_dwc3_ep0state_t; 215 216 typedef struct { 217 /* 218 * Kept at top to avoid struct size wastage since bounce_buf 219 * needs to be CACHE_LINE_SIZE aligned 220 */ 221 usb_dwc3_endpoint_bouncebuf_t bounce_bufs[USB_DWC3_NUM_OUT_EP]; 222 PCD_intbuffersdef intbuffers; 223 usb_dwc3_global_t *usb_global; 224 usb_dwc3_device_t *usb_device; 225 usb_dwc3_endpoint_t IN_ep[USB_DWC3_NUM_IN_EP]; 226 usb_dwc3_endpoint_t OUT_ep[USB_DWC3_NUM_OUT_EP]; 227 228 usb_dwc3_state_t State; /*!< PCD communication state */ 229 usb_dwc3_ep0state_t EP0_State; /*!< EP0 State */ 230 231 uint8_t *setup_addr; /*!< Setup packet coherent address */ 232 uintptr_t setup_dma_addr; /*!< Setup packet buffer DMA Bus address */ 233 234 struct pcd_handle *pcd_handle; 235 } dwc3_handle_t; 236 237 void usb_dwc3_init_driver(struct usb_handle *usb_core_handle, 238 struct pcd_handle *pcd_handle, dwc3_handle_t *dwc3_handle, 239 void *base_addr); 240 241 #endif /* __USB_DWC3_H */ 242