xref: /rk3399_ARM-atf/include/drivers/st/stm32mp1_pwr.h (revision 4353bb20cc8937a5d540a06c4a8fe7ee880fc3ca)
1*4353bb20SYann Gautier /*
2*4353bb20SYann Gautier  * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
3*4353bb20SYann Gautier  *
4*4353bb20SYann Gautier  * SPDX-License-Identifier: BSD-3-Clause
5*4353bb20SYann Gautier  */
6*4353bb20SYann Gautier 
7*4353bb20SYann Gautier #ifndef __STM32MP1_PWR_H__
8*4353bb20SYann Gautier #define __STM32MP1_PWR_H__
9*4353bb20SYann Gautier 
10*4353bb20SYann Gautier #include <utils_def.h>
11*4353bb20SYann Gautier 
12*4353bb20SYann Gautier #define PWR_CR1			U(0x00)
13*4353bb20SYann Gautier #define PWR_CR2			U(0x08)
14*4353bb20SYann Gautier #define PWR_CR3			U(0x0C)
15*4353bb20SYann Gautier #define PWR_MPUCR		U(0x10)
16*4353bb20SYann Gautier #define PWR_WKUPCR		U(0x20)
17*4353bb20SYann Gautier #define PWR_MPUWKUPENR		U(0x28)
18*4353bb20SYann Gautier 
19*4353bb20SYann Gautier #define PWR_CR1_LPDS		BIT(0)
20*4353bb20SYann Gautier #define PWR_CR1_LPCFG		BIT(1)
21*4353bb20SYann Gautier #define PWR_CR1_LVDS		BIT(2)
22*4353bb20SYann Gautier #define PWR_CR1_DBP		BIT(8)
23*4353bb20SYann Gautier 
24*4353bb20SYann Gautier #define PWR_CR3_DDRSREN		BIT(10)
25*4353bb20SYann Gautier #define PWR_CR3_DDRSRDIS	BIT(11)
26*4353bb20SYann Gautier #define PWR_CR3_DDRRETEN	BIT(12)
27*4353bb20SYann Gautier 
28*4353bb20SYann Gautier #define PWR_MPUCR_PDDS		BIT(0)
29*4353bb20SYann Gautier #define PWR_MPUCR_CSTDBYDIS	BIT(3)
30*4353bb20SYann Gautier #define PWR_MPUCR_CSSF		BIT(9)
31*4353bb20SYann Gautier 
32*4353bb20SYann Gautier #endif /* __STM32MP1_PWR_H__ */
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