1*165ad556SNicolas Le Bayon /* 2*165ad556SNicolas Le Bayon * Copyright (c) 2021, STMicroelectronics - All Rights Reserved 3*165ad556SNicolas Le Bayon * 4*165ad556SNicolas Le Bayon * SPDX-License-Identifier: BSD-3-Clause 5*165ad556SNicolas Le Bayon */ 6*165ad556SNicolas Le Bayon 7*165ad556SNicolas Le Bayon #ifndef STM32_UART_H 8*165ad556SNicolas Le Bayon #define STM32_UART_H 9*165ad556SNicolas Le Bayon 10*165ad556SNicolas Le Bayon /* UART word length */ 11*165ad556SNicolas Le Bayon #define STM32_UART_WORDLENGTH_7B USART_CR1_M1 12*165ad556SNicolas Le Bayon #define STM32_UART_WORDLENGTH_8B 0x00000000U 13*165ad556SNicolas Le Bayon #define STM32_UART_WORDLENGTH_9B USART_CR1_M0 14*165ad556SNicolas Le Bayon 15*165ad556SNicolas Le Bayon /* UART number of stop bits */ 16*165ad556SNicolas Le Bayon #define STM32_UART_STOPBITS_0_5 USART_CR2_STOP_0 17*165ad556SNicolas Le Bayon #define STM32_UART_STOPBITS_1 0x00000000U 18*165ad556SNicolas Le Bayon #define STM32_UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) 19*165ad556SNicolas Le Bayon #define STM32_UART_STOPBITS_2 USART_CR2_STOP_1 20*165ad556SNicolas Le Bayon 21*165ad556SNicolas Le Bayon /* UART parity */ 22*165ad556SNicolas Le Bayon #define STM32_UART_PARITY_NONE 0x00000000U 23*165ad556SNicolas Le Bayon #define STM32_UART_PARITY_EVEN USART_CR1_PCE 24*165ad556SNicolas Le Bayon #define STM32_UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) 25*165ad556SNicolas Le Bayon 26*165ad556SNicolas Le Bayon /* UART transfer mode */ 27*165ad556SNicolas Le Bayon #define STM32_UART_MODE_RX USART_CR1_RE 28*165ad556SNicolas Le Bayon #define STM32_UART_MODE_TX USART_CR1_TE 29*165ad556SNicolas Le Bayon #define STM32_UART_MODE_TX_RX (USART_CR1_TE | USART_CR1_RE) 30*165ad556SNicolas Le Bayon 31*165ad556SNicolas Le Bayon /* UART hardware flow control */ 32*165ad556SNicolas Le Bayon #define STM32_UART_HWCONTROL_NONE 0x00000000U 33*165ad556SNicolas Le Bayon #define STM32_UART_HWCONTROL_RTS USART_CR3_RTSE 34*165ad556SNicolas Le Bayon #define STM32_UART_HWCONTROL_CTS USART_CR3_CTSE 35*165ad556SNicolas Le Bayon #define STM32_UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) 36*165ad556SNicolas Le Bayon 37*165ad556SNicolas Le Bayon /* UART over sampling */ 38*165ad556SNicolas Le Bayon #define STM32_UART_OVERSAMPLING_16 0x00000000U 39*165ad556SNicolas Le Bayon #define STM32_UART_OVERSAMPLING_8 USART_CR1_OVER8 40*165ad556SNicolas Le Bayon 41*165ad556SNicolas Le Bayon /* UART prescaler */ 42*165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV1 0x00000000U 43*165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV2 0x00000001U 44*165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV4 0x00000002U 45*165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV6 0x00000003U 46*165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV8 0x00000004U 47*165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV10 0x00000005U 48*165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV12 0x00000006U 49*165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV16 0x00000007U 50*165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV32 0x00000008U 51*165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV64 0x00000009U 52*165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV128 0x0000000AU 53*165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV256 0x0000000BU 54*165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_NB 0x0000000CU 55*165ad556SNicolas Le Bayon 56*165ad556SNicolas Le Bayon /* UART fifo mode */ 57*165ad556SNicolas Le Bayon #define STM32_UART_FIFOMODE_EN USART_CR1_FIFOEN 58*165ad556SNicolas Le Bayon #define STM32_UART_FIFOMODE_DIS 0x00000000U 59*165ad556SNicolas Le Bayon 60*165ad556SNicolas Le Bayon /* UART TXFIFO threshold level */ 61*165ad556SNicolas Le Bayon #define STM32_UART_TXFIFO_THRESHOLD_1EIGHTHFULL 0x00000000U 62*165ad556SNicolas Le Bayon #define STM32_UART_TXFIFO_THRESHOLD_1QUARTERFUL USART_CR3_TXFTCFG_0 63*165ad556SNicolas Le Bayon #define STM32_UART_TXFIFO_THRESHOLD_HALFFULL USART_CR3_TXFTCFG_1 64*165ad556SNicolas Le Bayon #define STM32_UART_TXFIFO_THRESHOLD_3QUARTERSFULL (USART_CR3_TXFTCFG_0 | USART_CR3_TXFTCFG_1) 65*165ad556SNicolas Le Bayon #define STM32_UART_TXFIFO_THRESHOLD_7EIGHTHFULL USART_CR3_TXFTCFG_2 66*165ad556SNicolas Le Bayon #define STM32_UART_TXFIFO_THRESHOLD_EMPTY (USART_CR3_TXFTCFG_2 | USART_CR3_TXFTCFG_0) 67*165ad556SNicolas Le Bayon 68*165ad556SNicolas Le Bayon /* UART RXFIFO threshold level */ 69*165ad556SNicolas Le Bayon #define STM32_UART_RXFIFO_THRESHOLD_1EIGHTHFULL 0x00000000U 70*165ad556SNicolas Le Bayon #define STM32_UART_RXFIFO_THRESHOLD_1QUARTERFULL USART_CR3_RXFTCFG_0 71*165ad556SNicolas Le Bayon #define STM32_UART_RXFIFO_THRESHOLD_HALFFULL USART_CR3_RXFTCFG_1 72*165ad556SNicolas Le Bayon #define STM32_UART_RXFIFO_THRESHOLD_3QUARTERSFULL (USART_CR3_RXFTCFG_0 | USART_CR3_RXFTCFG_1) 73*165ad556SNicolas Le Bayon #define STM32_UART_RXFIFO_THRESHOLD_7EIGHTHFULL USART_CR3_RXFTCFG_2 74*165ad556SNicolas Le Bayon #define STM32_UART_RXFIFO_THRESHOLD_FULL (USART_CR3_RXFTCFG_2 | USART_CR3_RXFTCFG_0) 75*165ad556SNicolas Le Bayon 76*165ad556SNicolas Le Bayon struct stm32_uart_init_s { 77*165ad556SNicolas Le Bayon uint32_t baud_rate; /* 78*165ad556SNicolas Le Bayon * Configures the UART communication 79*165ad556SNicolas Le Bayon * baud rate. 80*165ad556SNicolas Le Bayon */ 81*165ad556SNicolas Le Bayon 82*165ad556SNicolas Le Bayon uint32_t word_length; /* 83*165ad556SNicolas Le Bayon * Specifies the number of data bits 84*165ad556SNicolas Le Bayon * transmitted or received in a frame. 85*165ad556SNicolas Le Bayon * This parameter can be a value of 86*165ad556SNicolas Le Bayon * @ref STM32_UART_WORDLENGTH_*. 87*165ad556SNicolas Le Bayon */ 88*165ad556SNicolas Le Bayon 89*165ad556SNicolas Le Bayon uint32_t stop_bits; /* 90*165ad556SNicolas Le Bayon * Specifies the number of stop bits 91*165ad556SNicolas Le Bayon * transmitted. This parameter can be 92*165ad556SNicolas Le Bayon * a value of @ref STM32_UART_STOPBITS_*. 93*165ad556SNicolas Le Bayon */ 94*165ad556SNicolas Le Bayon 95*165ad556SNicolas Le Bayon uint32_t parity; /* 96*165ad556SNicolas Le Bayon * Specifies the parity mode. 97*165ad556SNicolas Le Bayon * This parameter can be a value of 98*165ad556SNicolas Le Bayon * @ref STM32_UART_PARITY_*. 99*165ad556SNicolas Le Bayon */ 100*165ad556SNicolas Le Bayon 101*165ad556SNicolas Le Bayon uint32_t mode; /* 102*165ad556SNicolas Le Bayon * Specifies whether the receive or 103*165ad556SNicolas Le Bayon * transmit mode is enabled or 104*165ad556SNicolas Le Bayon * disabled. This parameter can be a 105*165ad556SNicolas Le Bayon * value of @ref @ref STM32_UART_MODE_*. 106*165ad556SNicolas Le Bayon */ 107*165ad556SNicolas Le Bayon 108*165ad556SNicolas Le Bayon uint32_t hw_flow_control; /* 109*165ad556SNicolas Le Bayon * Specifies whether the hardware flow 110*165ad556SNicolas Le Bayon * control mode is enabled or 111*165ad556SNicolas Le Bayon * disabled. This parameter can be a 112*165ad556SNicolas Le Bayon * value of @ref STM32_UARTHWCONTROL_*. 113*165ad556SNicolas Le Bayon */ 114*165ad556SNicolas Le Bayon 115*165ad556SNicolas Le Bayon uint32_t over_sampling; /* 116*165ad556SNicolas Le Bayon * Specifies whether the over sampling 117*165ad556SNicolas Le Bayon * 8 is enabled or disabled. 118*165ad556SNicolas Le Bayon * This parameter can be a value of 119*165ad556SNicolas Le Bayon * @ref STM32_UART_OVERSAMPLING_*. 120*165ad556SNicolas Le Bayon */ 121*165ad556SNicolas Le Bayon 122*165ad556SNicolas Le Bayon uint32_t one_bit_sampling; /* 123*165ad556SNicolas Le Bayon * Specifies whether a single sample 124*165ad556SNicolas Le Bayon * or three samples' majority vote is 125*165ad556SNicolas Le Bayon * selected. This parameter can be 0 126*165ad556SNicolas Le Bayon * or USART_CR3_ONEBIT. 127*165ad556SNicolas Le Bayon */ 128*165ad556SNicolas Le Bayon 129*165ad556SNicolas Le Bayon uint32_t prescaler; /* 130*165ad556SNicolas Le Bayon * Specifies the prescaler value used 131*165ad556SNicolas Le Bayon * to divide the UART clock source. 132*165ad556SNicolas Le Bayon * This parameter can be a value of 133*165ad556SNicolas Le Bayon * @ref STM32_UART_PRESCALER_*. 134*165ad556SNicolas Le Bayon */ 135*165ad556SNicolas Le Bayon 136*165ad556SNicolas Le Bayon uint32_t fifo_mode; /* 137*165ad556SNicolas Le Bayon * Specifies if the FIFO mode will be 138*165ad556SNicolas Le Bayon * used. This parameter can be a value 139*165ad556SNicolas Le Bayon * of @ref STM32_UART_FIFOMODE_*. 140*165ad556SNicolas Le Bayon */ 141*165ad556SNicolas Le Bayon 142*165ad556SNicolas Le Bayon uint32_t tx_fifo_threshold; /* 143*165ad556SNicolas Le Bayon * Specifies the TXFIFO threshold 144*165ad556SNicolas Le Bayon * level. This parameter can be a 145*165ad556SNicolas Le Bayon * value of @ref 146*165ad556SNicolas Le Bayon * STM32_UART_TXFIFO_THRESHOLD_*. 147*165ad556SNicolas Le Bayon */ 148*165ad556SNicolas Le Bayon 149*165ad556SNicolas Le Bayon uint32_t rx_fifo_threshold; /* 150*165ad556SNicolas Le Bayon * Specifies the RXFIFO threshold 151*165ad556SNicolas Le Bayon * level. This parameter can be a 152*165ad556SNicolas Le Bayon * value of @ref 153*165ad556SNicolas Le Bayon * STM32_UART_RXFIFO_THRESHOLD_*. 154*165ad556SNicolas Le Bayon */ 155*165ad556SNicolas Le Bayon }; 156*165ad556SNicolas Le Bayon 157*165ad556SNicolas Le Bayon struct stm32_uart_handle_s { 158*165ad556SNicolas Le Bayon uint32_t base; 159*165ad556SNicolas Le Bayon uint32_t rdr_mask; 160*165ad556SNicolas Le Bayon }; 161*165ad556SNicolas Le Bayon 162*165ad556SNicolas Le Bayon int stm32_uart_init(struct stm32_uart_handle_s *huart, 163*165ad556SNicolas Le Bayon uintptr_t base_addr, 164*165ad556SNicolas Le Bayon const struct stm32_uart_init_s *init); 165*165ad556SNicolas Le Bayon void stm32_uart_stop(uintptr_t base_addr); 166*165ad556SNicolas Le Bayon int stm32_uart_putc(struct stm32_uart_handle_s *huart, int c); 167*165ad556SNicolas Le Bayon int stm32_uart_flush(struct stm32_uart_handle_s *huart); 168*165ad556SNicolas Le Bayon int stm32_uart_getc(struct stm32_uart_handle_s *huart); 169*165ad556SNicolas Le Bayon 170*165ad556SNicolas Le Bayon #endif /* STM32_UART_H */ 171