1165ad556SNicolas Le Bayon /* 2*12581895SPatrick Delaunay * Copyright (c) 2021-2022, STMicroelectronics - All Rights Reserved 3165ad556SNicolas Le Bayon * 4165ad556SNicolas Le Bayon * SPDX-License-Identifier: BSD-3-Clause 5165ad556SNicolas Le Bayon */ 6165ad556SNicolas Le Bayon 7165ad556SNicolas Le Bayon #ifndef STM32_UART_H 8165ad556SNicolas Le Bayon #define STM32_UART_H 9165ad556SNicolas Le Bayon 10165ad556SNicolas Le Bayon /* UART word length */ 11165ad556SNicolas Le Bayon #define STM32_UART_WORDLENGTH_7B USART_CR1_M1 12165ad556SNicolas Le Bayon #define STM32_UART_WORDLENGTH_8B 0x00000000U 13165ad556SNicolas Le Bayon #define STM32_UART_WORDLENGTH_9B USART_CR1_M0 14165ad556SNicolas Le Bayon 15165ad556SNicolas Le Bayon /* UART number of stop bits */ 16165ad556SNicolas Le Bayon #define STM32_UART_STOPBITS_0_5 USART_CR2_STOP_0 17165ad556SNicolas Le Bayon #define STM32_UART_STOPBITS_1 0x00000000U 18165ad556SNicolas Le Bayon #define STM32_UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) 19165ad556SNicolas Le Bayon #define STM32_UART_STOPBITS_2 USART_CR2_STOP_1 20165ad556SNicolas Le Bayon 21165ad556SNicolas Le Bayon /* UART parity */ 22165ad556SNicolas Le Bayon #define STM32_UART_PARITY_NONE 0x00000000U 23165ad556SNicolas Le Bayon #define STM32_UART_PARITY_EVEN USART_CR1_PCE 24165ad556SNicolas Le Bayon #define STM32_UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) 25165ad556SNicolas Le Bayon 26165ad556SNicolas Le Bayon /* UART transfer mode */ 27165ad556SNicolas Le Bayon #define STM32_UART_MODE_RX USART_CR1_RE 28165ad556SNicolas Le Bayon #define STM32_UART_MODE_TX USART_CR1_TE 29165ad556SNicolas Le Bayon #define STM32_UART_MODE_TX_RX (USART_CR1_TE | USART_CR1_RE) 30165ad556SNicolas Le Bayon 31165ad556SNicolas Le Bayon /* UART hardware flow control */ 32165ad556SNicolas Le Bayon #define STM32_UART_HWCONTROL_NONE 0x00000000U 33165ad556SNicolas Le Bayon #define STM32_UART_HWCONTROL_RTS USART_CR3_RTSE 34165ad556SNicolas Le Bayon #define STM32_UART_HWCONTROL_CTS USART_CR3_CTSE 35165ad556SNicolas Le Bayon #define STM32_UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) 36165ad556SNicolas Le Bayon 37165ad556SNicolas Le Bayon /* UART prescaler */ 38165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV1 0x00000000U 39165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV2 0x00000001U 40165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV4 0x00000002U 41165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV6 0x00000003U 42165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV8 0x00000004U 43165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV10 0x00000005U 44165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV12 0x00000006U 45165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV16 0x00000007U 46165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV32 0x00000008U 47165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV64 0x00000009U 48165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV128 0x0000000AU 49165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_DIV256 0x0000000BU 50165ad556SNicolas Le Bayon #define STM32_UART_PRESCALER_NB 0x0000000CU 51165ad556SNicolas Le Bayon 52165ad556SNicolas Le Bayon /* UART fifo mode */ 53165ad556SNicolas Le Bayon #define STM32_UART_FIFOMODE_EN USART_CR1_FIFOEN 54165ad556SNicolas Le Bayon #define STM32_UART_FIFOMODE_DIS 0x00000000U 55165ad556SNicolas Le Bayon 56165ad556SNicolas Le Bayon /* UART TXFIFO threshold level */ 57165ad556SNicolas Le Bayon #define STM32_UART_TXFIFO_THRESHOLD_1EIGHTHFULL 0x00000000U 58165ad556SNicolas Le Bayon #define STM32_UART_TXFIFO_THRESHOLD_1QUARTERFUL USART_CR3_TXFTCFG_0 59165ad556SNicolas Le Bayon #define STM32_UART_TXFIFO_THRESHOLD_HALFFULL USART_CR3_TXFTCFG_1 60165ad556SNicolas Le Bayon #define STM32_UART_TXFIFO_THRESHOLD_3QUARTERSFULL (USART_CR3_TXFTCFG_0 | USART_CR3_TXFTCFG_1) 61165ad556SNicolas Le Bayon #define STM32_UART_TXFIFO_THRESHOLD_7EIGHTHFULL USART_CR3_TXFTCFG_2 62165ad556SNicolas Le Bayon #define STM32_UART_TXFIFO_THRESHOLD_EMPTY (USART_CR3_TXFTCFG_2 | USART_CR3_TXFTCFG_0) 63165ad556SNicolas Le Bayon 64165ad556SNicolas Le Bayon /* UART RXFIFO threshold level */ 65165ad556SNicolas Le Bayon #define STM32_UART_RXFIFO_THRESHOLD_1EIGHTHFULL 0x00000000U 66165ad556SNicolas Le Bayon #define STM32_UART_RXFIFO_THRESHOLD_1QUARTERFULL USART_CR3_RXFTCFG_0 67165ad556SNicolas Le Bayon #define STM32_UART_RXFIFO_THRESHOLD_HALFFULL USART_CR3_RXFTCFG_1 68165ad556SNicolas Le Bayon #define STM32_UART_RXFIFO_THRESHOLD_3QUARTERSFULL (USART_CR3_RXFTCFG_0 | USART_CR3_RXFTCFG_1) 69165ad556SNicolas Le Bayon #define STM32_UART_RXFIFO_THRESHOLD_7EIGHTHFULL USART_CR3_RXFTCFG_2 70165ad556SNicolas Le Bayon #define STM32_UART_RXFIFO_THRESHOLD_FULL (USART_CR3_RXFTCFG_2 | USART_CR3_RXFTCFG_0) 71165ad556SNicolas Le Bayon 72165ad556SNicolas Le Bayon struct stm32_uart_init_s { 73165ad556SNicolas Le Bayon uint32_t baud_rate; /* 74165ad556SNicolas Le Bayon * Configures the UART communication 75165ad556SNicolas Le Bayon * baud rate. 76165ad556SNicolas Le Bayon */ 77165ad556SNicolas Le Bayon 78165ad556SNicolas Le Bayon uint32_t word_length; /* 79165ad556SNicolas Le Bayon * Specifies the number of data bits 80165ad556SNicolas Le Bayon * transmitted or received in a frame. 81165ad556SNicolas Le Bayon * This parameter can be a value of 82165ad556SNicolas Le Bayon * @ref STM32_UART_WORDLENGTH_*. 83165ad556SNicolas Le Bayon */ 84165ad556SNicolas Le Bayon 85165ad556SNicolas Le Bayon uint32_t stop_bits; /* 86165ad556SNicolas Le Bayon * Specifies the number of stop bits 87165ad556SNicolas Le Bayon * transmitted. This parameter can be 88165ad556SNicolas Le Bayon * a value of @ref STM32_UART_STOPBITS_*. 89165ad556SNicolas Le Bayon */ 90165ad556SNicolas Le Bayon 91165ad556SNicolas Le Bayon uint32_t parity; /* 92165ad556SNicolas Le Bayon * Specifies the parity mode. 93165ad556SNicolas Le Bayon * This parameter can be a value of 94165ad556SNicolas Le Bayon * @ref STM32_UART_PARITY_*. 95165ad556SNicolas Le Bayon */ 96165ad556SNicolas Le Bayon 97165ad556SNicolas Le Bayon uint32_t mode; /* 98165ad556SNicolas Le Bayon * Specifies whether the receive or 99165ad556SNicolas Le Bayon * transmit mode is enabled or 100165ad556SNicolas Le Bayon * disabled. This parameter can be a 101165ad556SNicolas Le Bayon * value of @ref @ref STM32_UART_MODE_*. 102165ad556SNicolas Le Bayon */ 103165ad556SNicolas Le Bayon 104165ad556SNicolas Le Bayon uint32_t hw_flow_control; /* 105165ad556SNicolas Le Bayon * Specifies whether the hardware flow 106165ad556SNicolas Le Bayon * control mode is enabled or 107165ad556SNicolas Le Bayon * disabled. This parameter can be a 108165ad556SNicolas Le Bayon * value of @ref STM32_UARTHWCONTROL_*. 109165ad556SNicolas Le Bayon */ 110165ad556SNicolas Le Bayon 111165ad556SNicolas Le Bayon uint32_t one_bit_sampling; /* 112165ad556SNicolas Le Bayon * Specifies whether a single sample 113165ad556SNicolas Le Bayon * or three samples' majority vote is 114165ad556SNicolas Le Bayon * selected. This parameter can be 0 115165ad556SNicolas Le Bayon * or USART_CR3_ONEBIT. 116165ad556SNicolas Le Bayon */ 117165ad556SNicolas Le Bayon 118165ad556SNicolas Le Bayon uint32_t prescaler; /* 119165ad556SNicolas Le Bayon * Specifies the prescaler value used 120165ad556SNicolas Le Bayon * to divide the UART clock source. 121165ad556SNicolas Le Bayon * This parameter can be a value of 122165ad556SNicolas Le Bayon * @ref STM32_UART_PRESCALER_*. 123165ad556SNicolas Le Bayon */ 124165ad556SNicolas Le Bayon 125165ad556SNicolas Le Bayon uint32_t fifo_mode; /* 126165ad556SNicolas Le Bayon * Specifies if the FIFO mode will be 127165ad556SNicolas Le Bayon * used. This parameter can be a value 128165ad556SNicolas Le Bayon * of @ref STM32_UART_FIFOMODE_*. 129165ad556SNicolas Le Bayon */ 130165ad556SNicolas Le Bayon 131165ad556SNicolas Le Bayon uint32_t tx_fifo_threshold; /* 132165ad556SNicolas Le Bayon * Specifies the TXFIFO threshold 133165ad556SNicolas Le Bayon * level. This parameter can be a 134165ad556SNicolas Le Bayon * value of @ref 135165ad556SNicolas Le Bayon * STM32_UART_TXFIFO_THRESHOLD_*. 136165ad556SNicolas Le Bayon */ 137165ad556SNicolas Le Bayon 138165ad556SNicolas Le Bayon uint32_t rx_fifo_threshold; /* 139165ad556SNicolas Le Bayon * Specifies the RXFIFO threshold 140165ad556SNicolas Le Bayon * level. This parameter can be a 141165ad556SNicolas Le Bayon * value of @ref 142165ad556SNicolas Le Bayon * STM32_UART_RXFIFO_THRESHOLD_*. 143165ad556SNicolas Le Bayon */ 144165ad556SNicolas Le Bayon }; 145165ad556SNicolas Le Bayon 146165ad556SNicolas Le Bayon struct stm32_uart_handle_s { 147165ad556SNicolas Le Bayon uint32_t base; 148165ad556SNicolas Le Bayon uint32_t rdr_mask; 149165ad556SNicolas Le Bayon }; 150165ad556SNicolas Le Bayon 151165ad556SNicolas Le Bayon int stm32_uart_init(struct stm32_uart_handle_s *huart, 152165ad556SNicolas Le Bayon uintptr_t base_addr, 153165ad556SNicolas Le Bayon const struct stm32_uart_init_s *init); 154165ad556SNicolas Le Bayon void stm32_uart_stop(uintptr_t base_addr); 155165ad556SNicolas Le Bayon int stm32_uart_putc(struct stm32_uart_handle_s *huart, int c); 156165ad556SNicolas Le Bayon int stm32_uart_flush(struct stm32_uart_handle_s *huart); 157165ad556SNicolas Le Bayon int stm32_uart_getc(struct stm32_uart_handle_s *huart); 158165ad556SNicolas Le Bayon 159165ad556SNicolas Le Bayon #endif /* STM32_UART_H */ 160