1*a13550d0SLionel Debieve /* 2*a13550d0SLionel Debieve * Copyright (c) 2019, STMicroelectronics - All Rights Reserved 3*a13550d0SLionel Debieve * 4*a13550d0SLionel Debieve * SPDX-License-Identifier: BSD-3-Clause 5*a13550d0SLionel Debieve */ 6*a13550d0SLionel Debieve 7*a13550d0SLionel Debieve #ifndef DRIVERS_SPI_NOR_H 8*a13550d0SLionel Debieve #define DRIVERS_SPI_NOR_H 9*a13550d0SLionel Debieve 10*a13550d0SLionel Debieve #include <drivers/spi_mem.h> 11*a13550d0SLionel Debieve 12*a13550d0SLionel Debieve /* OPCODE */ 13*a13550d0SLionel Debieve #define SPI_NOR_OP_WREN 0x06U /* Write enable */ 14*a13550d0SLionel Debieve #define SPI_NOR_OP_WRSR 0x01U /* Write status register 1 byte */ 15*a13550d0SLionel Debieve #define SPI_NOR_OP_READ_ID 0x9FU /* Read JEDEC ID */ 16*a13550d0SLionel Debieve #define SPI_NOR_OP_READ_CR 0x35U /* Read configuration register */ 17*a13550d0SLionel Debieve #define SPI_NOR_OP_READ_SR 0x05U /* Read status register */ 18*a13550d0SLionel Debieve #define SPI_NOR_OP_READ_FSR 0x70U /* Read flag status register */ 19*a13550d0SLionel Debieve #define SPINOR_OP_RDEAR 0xC8U /* Read Extended Address Register */ 20*a13550d0SLionel Debieve #define SPINOR_OP_WREAR 0xC5U /* Write Extended Address Register */ 21*a13550d0SLionel Debieve 22*a13550d0SLionel Debieve /* Used for Spansion flashes only. */ 23*a13550d0SLionel Debieve #define SPINOR_OP_BRWR 0x17U /* Bank register write */ 24*a13550d0SLionel Debieve #define SPINOR_OP_BRRD 0x16U /* Bank register read */ 25*a13550d0SLionel Debieve 26*a13550d0SLionel Debieve #define SPI_NOR_OP_READ 0x03U /* Read data bytes (low frequency) */ 27*a13550d0SLionel Debieve #define SPI_NOR_OP_READ_FAST 0x0BU /* Read data bytes (high frequency) */ 28*a13550d0SLionel Debieve #define SPI_NOR_OP_READ_1_1_2 0x3BU /* Read data bytes (Dual Output SPI) */ 29*a13550d0SLionel Debieve #define SPI_NOR_OP_READ_1_2_2 0xBBU /* Read data bytes (Dual I/O SPI) */ 30*a13550d0SLionel Debieve #define SPI_NOR_OP_READ_1_1_4 0x6BU /* Read data bytes (Quad Output SPI) */ 31*a13550d0SLionel Debieve #define SPI_NOR_OP_READ_1_4_4 0xEBU /* Read data bytes (Quad I/O SPI) */ 32*a13550d0SLionel Debieve 33*a13550d0SLionel Debieve /* Flags for NOR specific configuration */ 34*a13550d0SLionel Debieve #define SPI_NOR_USE_FSR BIT(0) 35*a13550d0SLionel Debieve #define SPI_NOR_USE_BANK BIT(1) 36*a13550d0SLionel Debieve 37*a13550d0SLionel Debieve struct nor_device { 38*a13550d0SLionel Debieve struct spi_mem_op read_op; 39*a13550d0SLionel Debieve uint32_t size; 40*a13550d0SLionel Debieve uint32_t flags; 41*a13550d0SLionel Debieve uint8_t selected_bank; 42*a13550d0SLionel Debieve uint8_t bank_write_cmd; 43*a13550d0SLionel Debieve uint8_t bank_read_cmd; 44*a13550d0SLionel Debieve }; 45*a13550d0SLionel Debieve 46*a13550d0SLionel Debieve int spi_nor_read(unsigned int offset, uintptr_t buffer, size_t length, 47*a13550d0SLionel Debieve size_t *length_read); 48*a13550d0SLionel Debieve int spi_nor_init(unsigned long long *device_size, unsigned int *erase_size); 49*a13550d0SLionel Debieve 50*a13550d0SLionel Debieve /* 51*a13550d0SLionel Debieve * Platform can implement this to override default NOR instance configuration. 52*a13550d0SLionel Debieve * 53*a13550d0SLionel Debieve * @device: target NOR instance. 54*a13550d0SLionel Debieve * Return 0 on success, negative value otherwise. 55*a13550d0SLionel Debieve */ 56*a13550d0SLionel Debieve int plat_get_nor_data(struct nor_device *device); 57*a13550d0SLionel Debieve 58*a13550d0SLionel Debieve #endif /* DRIVERS_SPI_NOR_H */ 59