1c3e57739SLionel Debieve /* 2*da7a33cfSChristophe Kerello * Copyright (c) 2019-2023, STMicroelectronics - All Rights Reserved 3c3e57739SLionel Debieve * 4c3e57739SLionel Debieve * SPDX-License-Identifier: BSD-3-Clause 5c3e57739SLionel Debieve */ 6c3e57739SLionel Debieve 7c3e57739SLionel Debieve #ifndef DRIVERS_SPI_NAND_H 8c3e57739SLionel Debieve #define DRIVERS_SPI_NAND_H 9c3e57739SLionel Debieve 10c3e57739SLionel Debieve #include <drivers/nand.h> 11c3e57739SLionel Debieve #include <drivers/spi_mem.h> 12c3e57739SLionel Debieve 13c3e57739SLionel Debieve #define SPI_NAND_OP_GET_FEATURE 0x0FU 14c3e57739SLionel Debieve #define SPI_NAND_OP_SET_FEATURE 0x1FU 15c3e57739SLionel Debieve #define SPI_NAND_OP_READ_ID 0x9FU 16c3e57739SLionel Debieve #define SPI_NAND_OP_LOAD_PAGE 0x13U 17c3e57739SLionel Debieve #define SPI_NAND_OP_RESET 0xFFU 18c3e57739SLionel Debieve #define SPI_NAND_OP_READ_FROM_CACHE 0x03U 19c3e57739SLionel Debieve #define SPI_NAND_OP_READ_FROM_CACHE_2X 0x3BU 20c3e57739SLionel Debieve #define SPI_NAND_OP_READ_FROM_CACHE_4X 0x6BU 21c3e57739SLionel Debieve 22c3e57739SLionel Debieve /* Configuration register */ 23c3e57739SLionel Debieve #define SPI_NAND_REG_CFG 0xB0U 24c3e57739SLionel Debieve #define SPI_NAND_CFG_ECC_EN BIT(4) 25c3e57739SLionel Debieve #define SPI_NAND_CFG_QE BIT(0) 26c3e57739SLionel Debieve 27c3e57739SLionel Debieve /* Status register */ 28c3e57739SLionel Debieve #define SPI_NAND_REG_STATUS 0xC0U 29c3e57739SLionel Debieve #define SPI_NAND_STATUS_BUSY BIT(0) 30c3e57739SLionel Debieve #define SPI_NAND_STATUS_ECC_UNCOR BIT(5) 31c3e57739SLionel Debieve 32*da7a33cfSChristophe Kerello /* Flags for specific configuration */ 33*da7a33cfSChristophe Kerello #define SPI_NAND_HAS_QE_BIT BIT(0) 34*da7a33cfSChristophe Kerello 35c3e57739SLionel Debieve struct spinand_device { 36c3e57739SLionel Debieve struct nand_device *nand_dev; 37c3e57739SLionel Debieve struct spi_mem_op spi_read_cache_op; 38*da7a33cfSChristophe Kerello uint32_t flags; 39c3e57739SLionel Debieve uint8_t cfg_cache; /* Cached value of SPI NAND device register CFG */ 40c3e57739SLionel Debieve }; 41c3e57739SLionel Debieve 42c3e57739SLionel Debieve int spi_nand_init(unsigned long long *size, unsigned int *erase_size); 43c3e57739SLionel Debieve 44c3e57739SLionel Debieve /* 45c3e57739SLionel Debieve * Platform can implement this to override default SPI-NAND instance 46c3e57739SLionel Debieve * configuration. 47c3e57739SLionel Debieve * 48c3e57739SLionel Debieve * @device: target SPI-NAND instance. 49c3e57739SLionel Debieve * Return 0 on success, negative value otherwise. 50c3e57739SLionel Debieve */ 51c3e57739SLionel Debieve int plat_get_spi_nand_data(struct spinand_device *device); 52c3e57739SLionel Debieve 53c3e57739SLionel Debieve #endif /* DRIVERS_SPI_NAND_H */ 54