1*050a99a6SPankaj Gupta /* 2*050a99a6SPankaj Gupta * Copyright 2021 NXP 3*050a99a6SPankaj Gupta * 4*050a99a6SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5*050a99a6SPankaj Gupta * 6*050a99a6SPankaj Gupta */ 7*050a99a6SPankaj Gupta 8*050a99a6SPankaj Gupta #if !defined(PLAT_TZC400_H) && defined(IMAGE_BL2) 9*050a99a6SPankaj Gupta #define PLAT_TZC400_H 10*050a99a6SPankaj Gupta 11*050a99a6SPankaj Gupta #include <tzc400.h> 12*050a99a6SPankaj Gupta 13*050a99a6SPankaj Gupta /* Structure to configure TZC Regions' boundaries and attributes. */ 14*050a99a6SPankaj Gupta struct tzc400_reg { 15*050a99a6SPankaj Gupta uint8_t reg_filter_en; 16*050a99a6SPankaj Gupta unsigned long long start_addr; 17*050a99a6SPankaj Gupta unsigned long long end_addr; 18*050a99a6SPankaj Gupta unsigned int sec_attr; 19*050a99a6SPankaj Gupta unsigned int nsaid_permissions; 20*050a99a6SPankaj Gupta }; 21*050a99a6SPankaj Gupta 22*050a99a6SPankaj Gupta #define TZC_REGION_NS_NONE 0x00000000U 23*050a99a6SPankaj Gupta 24*050a99a6SPankaj Gupta /* NXP Platforms do not support NS Access ID (NSAID) based non-secure access. 25*050a99a6SPankaj Gupta * Supports only non secure through generic NS ACCESS ID 26*050a99a6SPankaj Gupta */ 27*050a99a6SPankaj Gupta #define TZC_NS_ACCESS_ID 0xFFFFFFFFU 28*050a99a6SPankaj Gupta 29*050a99a6SPankaj Gupta /* Number of DRAM regions to be configured 30*050a99a6SPankaj Gupta * for the platform can be over-written. 31*050a99a6SPankaj Gupta * 32*050a99a6SPankaj Gupta * Array tzc400_reg_list too, needs be over-written 33*050a99a6SPankaj Gupta * if there is any changes to default DRAM region 34*050a99a6SPankaj Gupta * configuration. 35*050a99a6SPankaj Gupta */ 36*050a99a6SPankaj Gupta #ifndef MAX_NUM_TZC_REGION 37*050a99a6SPankaj Gupta /* 3 regions: 38*050a99a6SPankaj Gupta * Region 0(default), 39*050a99a6SPankaj Gupta * Region 1 (DRAM0, Secure Memory), 40*050a99a6SPankaj Gupta * Region 2 (DRAM0, Shared memory) 41*050a99a6SPankaj Gupta */ 42*050a99a6SPankaj Gupta #define MAX_NUM_TZC_REGION NUM_DRAM_REGIONS + 3 43*050a99a6SPankaj Gupta #define DEFAULT_TZASC_CONFIG 1 44*050a99a6SPankaj Gupta #endif 45*050a99a6SPankaj Gupta 46*050a99a6SPankaj Gupta void mem_access_setup(uintptr_t base, uint32_t total_regions, 47*050a99a6SPankaj Gupta struct tzc400_reg *tzc400_reg_list); 48*050a99a6SPankaj Gupta int populate_tzc400_reg_list(struct tzc400_reg *tzc400_reg_list, 49*050a99a6SPankaj Gupta int dram_idx, int list_idx, 50*050a99a6SPankaj Gupta uint64_t dram_start_addr, 51*050a99a6SPankaj Gupta uint64_t dram_size, 52*050a99a6SPankaj Gupta uint32_t secure_dram_sz, 53*050a99a6SPankaj Gupta uint32_t shrd_dram_sz); 54*050a99a6SPankaj Gupta 55*050a99a6SPankaj Gupta #endif /* PLAT_TZC400_H */ 56