1*de9e57ffSJiafei Pan /* 2*de9e57ffSJiafei Pan * Copyright 2018-2021 NXP 3*de9e57ffSJiafei Pan * 4*de9e57ffSJiafei Pan * SPDX-License-Identifier: BSD-3-Clause 5*de9e57ffSJiafei Pan */ 6*de9e57ffSJiafei Pan 7*de9e57ffSJiafei Pan #if !defined(PLAT_TZC380_H) && defined(IMAGE_BL2) 8*de9e57ffSJiafei Pan #define PLAT_TZC380_H 9*de9e57ffSJiafei Pan 10*de9e57ffSJiafei Pan #include <tzc380.h> 11*de9e57ffSJiafei Pan 12*de9e57ffSJiafei Pan /* Number of DRAM regions to be configured 13*de9e57ffSJiafei Pan * for the platform can be over-written. 14*de9e57ffSJiafei Pan * 15*de9e57ffSJiafei Pan * Array tzc400_reg_list too, needs be over-written 16*de9e57ffSJiafei Pan * if there is any changes to default DRAM region 17*de9e57ffSJiafei Pan * configuration. 18*de9e57ffSJiafei Pan */ 19*de9e57ffSJiafei Pan #ifndef MAX_NUM_TZC_REGION 20*de9e57ffSJiafei Pan /* 3 regions: 21*de9e57ffSJiafei Pan * Region 0(default), 22*de9e57ffSJiafei Pan * Region 1 (DRAM0, Secure Memory), 23*de9e57ffSJiafei Pan * Region 2 (DRAM0, Shared memory) 24*de9e57ffSJiafei Pan */ 25*de9e57ffSJiafei Pan #define MAX_NUM_TZC_REGION 3 26*de9e57ffSJiafei Pan #define DEFAULT_TZASC_CONFIG 1 27*de9e57ffSJiafei Pan #endif 28*de9e57ffSJiafei Pan 29*de9e57ffSJiafei Pan struct tzc380_reg { 30*de9e57ffSJiafei Pan unsigned int secure; 31*de9e57ffSJiafei Pan unsigned int enabled; 32*de9e57ffSJiafei Pan uint64_t addr; 33*de9e57ffSJiafei Pan uint64_t size; 34*de9e57ffSJiafei Pan unsigned int sub_mask; 35*de9e57ffSJiafei Pan }; 36*de9e57ffSJiafei Pan 37*de9e57ffSJiafei Pan void mem_access_setup(uintptr_t base, uint32_t total_regions, 38*de9e57ffSJiafei Pan struct tzc380_reg *tzc380_reg_list); 39*de9e57ffSJiafei Pan 40*de9e57ffSJiafei Pan int populate_tzc380_reg_list(struct tzc380_reg *tzc380_reg_list, 41*de9e57ffSJiafei Pan int dram_idx, int list_idx, 42*de9e57ffSJiafei Pan uint64_t dram_start_addr, 43*de9e57ffSJiafei Pan uint64_t dram_size, 44*de9e57ffSJiafei Pan uint32_t secure_dram_sz, 45*de9e57ffSJiafei Pan uint32_t shrd_dram_sz); 46*de9e57ffSJiafei Pan 47*de9e57ffSJiafei Pan #endif /* PLAT_TZC380_H */ 48