1*050a99a6SPankaj Gupta /* 2*050a99a6SPankaj Gupta * Copyright 2021 NXP 3*050a99a6SPankaj Gupta * 4*050a99a6SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5*050a99a6SPankaj Gupta * 6*050a99a6SPankaj Gupta */ 7*050a99a6SPankaj Gupta 8*050a99a6SPankaj Gupta # 9*050a99a6SPankaj Gupta #ifndef NXP_TIMER_H 10*050a99a6SPankaj Gupta #define NXP_TIMER_H 11*050a99a6SPankaj Gupta 12*050a99a6SPankaj Gupta /* System Counter Offset and Bit Mask */ 13*050a99a6SPankaj Gupta #define SYS_COUNTER_CNTCR_OFFSET 0x0 14*050a99a6SPankaj Gupta #define SYS_COUNTER_CNTCR_EN 0x00000001 15*050a99a6SPankaj Gupta #define CNTCR_EN_MASK 0x1 16*050a99a6SPankaj Gupta 17*050a99a6SPankaj Gupta #ifndef __ASSEMBLER__ 18*050a99a6SPankaj Gupta uint64_t get_timer_val(uint64_t start); 19*050a99a6SPankaj Gupta 20*050a99a6SPankaj Gupta #ifdef IMAGE_BL31 21*050a99a6SPankaj Gupta void ls_configure_sys_timer(uintptr_t ls_sys_timctl_base, 22*050a99a6SPankaj Gupta uint8_t ls_config_cntacr, 23*050a99a6SPankaj Gupta uint8_t plat_ls_ns_timer_frame_id); 24*050a99a6SPankaj Gupta void enable_init_timer(void); 25*050a99a6SPankaj Gupta #endif 26*050a99a6SPankaj Gupta 27*050a99a6SPankaj Gupta /* 28*050a99a6SPankaj Gupta * Initialise the nxp on-chip free rolling usec counter as the delay 29*050a99a6SPankaj Gupta * timer. 30*050a99a6SPankaj Gupta */ 31*050a99a6SPankaj Gupta void delay_timer_init(uintptr_t nxp_timer_addr); 32*050a99a6SPankaj Gupta void ls_bl31_timer_init(uintptr_t nxp_timer_addr); 33*050a99a6SPankaj Gupta #endif /* __ASSEMBLER__ */ 34*050a99a6SPankaj Gupta 35*050a99a6SPankaj Gupta #endif /* NXP_TIMER_H */ 36