1*39faa9b2SPankaj Gupta /* 2*39faa9b2SPankaj Gupta * Copyright 2018-2020 NXP 3*39faa9b2SPankaj Gupta * 4*39faa9b2SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5*39faa9b2SPankaj Gupta * 6*39faa9b2SPankaj Gupta */ 7*39faa9b2SPankaj Gupta 8*39faa9b2SPankaj Gupta #ifndef NXP_SMMU_H 9*39faa9b2SPankaj Gupta #define NXP_SMMU_H 10*39faa9b2SPankaj Gupta 11*39faa9b2SPankaj Gupta #define SMMU_SCR0 (0x0) 12*39faa9b2SPankaj Gupta #define SMMU_NSCR0 (0x400) 13*39faa9b2SPankaj Gupta 14*39faa9b2SPankaj Gupta #define SCR0_CLIENTPD_MASK 0x00000001 15*39faa9b2SPankaj Gupta #define SCR0_USFCFG_MASK 0x00000400 16*39faa9b2SPankaj Gupta 17*39faa9b2SPankaj Gupta static inline void bypass_smmu(uintptr_t smmu_base_addr) 18*39faa9b2SPankaj Gupta { 19*39faa9b2SPankaj Gupta uint32_t val; 20*39faa9b2SPankaj Gupta 21*39faa9b2SPankaj Gupta val = (mmio_read_32(smmu_base_addr + SMMU_SCR0) | SCR0_CLIENTPD_MASK) & 22*39faa9b2SPankaj Gupta ~(SCR0_USFCFG_MASK); 23*39faa9b2SPankaj Gupta mmio_write_32((smmu_base_addr + SMMU_SCR0), val); 24*39faa9b2SPankaj Gupta 25*39faa9b2SPankaj Gupta val = (mmio_read_32(smmu_base_addr + SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & 26*39faa9b2SPankaj Gupta ~(SCR0_USFCFG_MASK); 27*39faa9b2SPankaj Gupta mmio_write_32((smmu_base_addr + SMMU_NSCR0), val); 28*39faa9b2SPankaj Gupta } 29*39faa9b2SPankaj Gupta 30*39faa9b2SPankaj Gupta #endif 31