139faa9b2SPankaj Gupta /* 239faa9b2SPankaj Gupta * Copyright 2018-2020 NXP 339faa9b2SPankaj Gupta * 439faa9b2SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 539faa9b2SPankaj Gupta * 639faa9b2SPankaj Gupta */ 739faa9b2SPankaj Gupta 839faa9b2SPankaj Gupta #ifndef NXP_SMMU_H 939faa9b2SPankaj Gupta #define NXP_SMMU_H 1039faa9b2SPankaj Gupta 1139faa9b2SPankaj Gupta #define SMMU_SCR0 (0x0) 1239faa9b2SPankaj Gupta #define SMMU_NSCR0 (0x400) 13*0ca1d8fbSHoward Lu #define SMMU_SACR (0x10) 1439faa9b2SPankaj Gupta 1539faa9b2SPankaj Gupta #define SCR0_CLIENTPD_MASK 0x00000001 1639faa9b2SPankaj Gupta #define SCR0_USFCFG_MASK 0x00000400 1739faa9b2SPankaj Gupta 18*0ca1d8fbSHoward Lu #define SMMU_SACR_CACHE_LOCK_ENABLE_BIT (1ULL << 26U) 19*0ca1d8fbSHoward Lu bypass_smmu(uintptr_t smmu_base_addr)2039faa9b2SPankaj Guptastatic inline void bypass_smmu(uintptr_t smmu_base_addr) 2139faa9b2SPankaj Gupta { 2239faa9b2SPankaj Gupta uint32_t val; 2339faa9b2SPankaj Gupta 2439faa9b2SPankaj Gupta val = (mmio_read_32(smmu_base_addr + SMMU_SCR0) | SCR0_CLIENTPD_MASK) & 2539faa9b2SPankaj Gupta ~(SCR0_USFCFG_MASK); 2639faa9b2SPankaj Gupta mmio_write_32((smmu_base_addr + SMMU_SCR0), val); 2739faa9b2SPankaj Gupta 2839faa9b2SPankaj Gupta val = (mmio_read_32(smmu_base_addr + SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & 2939faa9b2SPankaj Gupta ~(SCR0_USFCFG_MASK); 3039faa9b2SPankaj Gupta mmio_write_32((smmu_base_addr + SMMU_NSCR0), val); 3139faa9b2SPankaj Gupta } 3239faa9b2SPankaj Gupta smmu_cache_unlock(uintptr_t smmu_base_addr)33*0ca1d8fbSHoward Lustatic inline void smmu_cache_unlock(uintptr_t smmu_base_addr) 34*0ca1d8fbSHoward Lu { 35*0ca1d8fbSHoward Lu uint32_t val; 36*0ca1d8fbSHoward Lu 37*0ca1d8fbSHoward Lu val = mmio_read_32((smmu_base_addr + SMMU_SACR)); 38*0ca1d8fbSHoward Lu val &= (uint32_t)~SMMU_SACR_CACHE_LOCK_ENABLE_BIT; 39*0ca1d8fbSHoward Lu mmio_write_32((smmu_base_addr + SMMU_SACR), val); 40*0ca1d8fbSHoward Lu } 41*0ca1d8fbSHoward Lu 4239faa9b2SPankaj Gupta #endif 43