1*050a99a6SPankaj Gupta /* 2*050a99a6SPankaj Gupta * Copyright 2021 NXP 3*050a99a6SPankaj Gupta * 4*050a99a6SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5*050a99a6SPankaj Gupta * 6*050a99a6SPankaj Gupta */ 7*050a99a6SPankaj Gupta 8*050a99a6SPankaj Gupta #ifndef SFP_H 9*050a99a6SPankaj Gupta #define SFP_H 10*050a99a6SPankaj Gupta 11*050a99a6SPankaj Gupta #include <endian.h> 12*050a99a6SPankaj Gupta #include <lib/mmio.h> 13*050a99a6SPankaj Gupta 14*050a99a6SPankaj Gupta /* SFP Configuration Register Offsets */ 15*050a99a6SPankaj Gupta #define SFP_INGR_OFFSET U(0x20) 16*050a99a6SPankaj Gupta #define SFP_SVHESR_OFFSET U(0x24) 17*050a99a6SPankaj Gupta #define SFP_SFPCR_OFFSET U(0x28) 18*050a99a6SPankaj Gupta #define SFP_VER_OFFSET U(0x38) 19*050a99a6SPankaj Gupta 20*050a99a6SPankaj Gupta /* SFP Hamming register masks for OTPMK and DRV */ 21*050a99a6SPankaj Gupta #define SFP_SVHESR_DRV_MASK U(0x7F) 22*050a99a6SPankaj Gupta #define SFP_SVHESR_OTPMK_MASK U(0x7FC00) 23*050a99a6SPankaj Gupta 24*050a99a6SPankaj Gupta /* SFP commands */ 25*050a99a6SPankaj Gupta #define SFP_INGR_READFB_CMD U(0x1) 26*050a99a6SPankaj Gupta #define SFP_INGR_PROGFB_CMD U(0x2) 27*050a99a6SPankaj Gupta #define SFP_INGR_ERROR_MASK U(0x100) 28*050a99a6SPankaj Gupta 29*050a99a6SPankaj Gupta /* SFPCR Masks */ 30*050a99a6SPankaj Gupta #define SFP_SFPCR_WD U(0x80000000) 31*050a99a6SPankaj Gupta #define SFP_SFPCR_WDL U(0x40000000) 32*050a99a6SPankaj Gupta 33*050a99a6SPankaj Gupta /* SFPCR Masks */ 34*050a99a6SPankaj Gupta #define SFP_SFPCR_WD U(0x80000000) 35*050a99a6SPankaj Gupta #define SFP_SFPCR_WDL U(0x40000000) 36*050a99a6SPankaj Gupta 37*050a99a6SPankaj Gupta #define SFP_FUSE_REGS_OFFSET U(0x200) 38*050a99a6SPankaj Gupta 39*050a99a6SPankaj Gupta #ifdef NXP_SFP_VER_3_4 40*050a99a6SPankaj Gupta #define OSPR0_SC_MASK U(0xC000FE35) 41*050a99a6SPankaj Gupta #elif defined(NXP_SFP_VER_3_2) 42*050a99a6SPankaj Gupta #define OSPR0_SC_MASK U(0x0000E035) 43*050a99a6SPankaj Gupta #endif 44*050a99a6SPankaj Gupta 45*050a99a6SPankaj Gupta #if defined(NXP_SFP_VER_3_4) 46*050a99a6SPankaj Gupta #define OSPR_KEY_REVOC_SHIFT U(9) 47*050a99a6SPankaj Gupta #define OSPR_KEY_REVOC_MASK U(0x0000fe00) 48*050a99a6SPankaj Gupta #elif defined(NXP_SFP_VER_3_2) 49*050a99a6SPankaj Gupta #define OSPR_KEY_REVOC_SHIFT U(13) 50*050a99a6SPankaj Gupta #define OSPR_KEY_REVOC_MASK U(0x0000e000) 51*050a99a6SPankaj Gupta #endif /* NXP_SFP_VER_3_4 */ 52*050a99a6SPankaj Gupta 53*050a99a6SPankaj Gupta #define OSPR1_MC_MASK U(0xFFFF0000) 54*050a99a6SPankaj Gupta #define OSPR1_DBG_LVL_MASK U(0x00000007) 55*050a99a6SPankaj Gupta 56*050a99a6SPankaj Gupta #define OSPR_ITS_MASK U(0x00000004) 57*050a99a6SPankaj Gupta #define OSPR_WP_MASK U(0x00000001) 58*050a99a6SPankaj Gupta 59*050a99a6SPankaj Gupta #define MAX_OEM_UID U(5) 60*050a99a6SPankaj Gupta #define SRK_HASH_SIZE U(32) 61*050a99a6SPankaj Gupta 62*050a99a6SPankaj Gupta /* SFP CCSR Register Map */ 63*050a99a6SPankaj Gupta struct sfp_ccsr_regs_t { 64*050a99a6SPankaj Gupta uint32_t ospr; /* 0x200 OSPR0 */ 65*050a99a6SPankaj Gupta uint32_t ospr1; /* 0x204 OSPR1 */ 66*050a99a6SPankaj Gupta uint32_t dcv[2]; /* 0x208 Debug Challenge Value */ 67*050a99a6SPankaj Gupta uint32_t drv[2]; /* 0x210 Debug Response Value */ 68*050a99a6SPankaj Gupta uint32_t fswpr; /* 0x218 FSL Section Write Protect */ 69*050a99a6SPankaj Gupta uint32_t fsl_uid[2]; /* 0x21c FSL UID 0 */ 70*050a99a6SPankaj Gupta uint32_t isbcr; /* 0x224 ISBC Configuration */ 71*050a99a6SPankaj Gupta uint32_t fsspr[3]; /* 0x228 FSL Scratch Pad */ 72*050a99a6SPankaj Gupta uint32_t otpmk[8]; /* 0x234 OTPMK */ 73*050a99a6SPankaj Gupta uint32_t srk_hash[SRK_HASH_SIZE/sizeof(uint32_t)]; 74*050a99a6SPankaj Gupta /* 0x254 Super Root Key Hash */ 75*050a99a6SPankaj Gupta uint32_t oem_uid[MAX_OEM_UID]; /* 0x274 OEM UID 0 */ 76*050a99a6SPankaj Gupta }; 77*050a99a6SPankaj Gupta 78*050a99a6SPankaj Gupta uintptr_t get_sfp_addr(void); 79*050a99a6SPankaj Gupta void sfp_init(uintptr_t nxp_sfp_addr); 80*050a99a6SPankaj Gupta uint32_t *get_sfp_srk_hash(void); 81*050a99a6SPankaj Gupta int sfp_check_its(void); 82*050a99a6SPankaj Gupta int sfp_check_oem_wp(void); 83*050a99a6SPankaj Gupta uint32_t get_key_revoc(void); 84*050a99a6SPankaj Gupta void set_sfp_wr_disable(void); 85*050a99a6SPankaj Gupta int sfp_program_fuses(void); 86*050a99a6SPankaj Gupta 87*050a99a6SPankaj Gupta uint32_t sfp_read_oem_uid(uint8_t oem_uid); 88*050a99a6SPankaj Gupta uint32_t sfp_write_oem_uid(uint8_t oem_uid, uint32_t sfp_val); 89*050a99a6SPankaj Gupta 90*050a99a6SPankaj Gupta #ifdef NXP_SFP_BE 91*050a99a6SPankaj Gupta #define sfp_read32(a) bswap32(mmio_read_32((uintptr_t)(a))) 92*050a99a6SPankaj Gupta #define sfp_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) 93*050a99a6SPankaj Gupta #elif defined(NXP_SFP_LE) 94*050a99a6SPankaj Gupta #define sfp_read32(a) mmio_read_32((uintptr_t)(a)) 95*050a99a6SPankaj Gupta #define sfp_write32(a, v) mmio_write_32((uintptr_t)(a), (v)) 96*050a99a6SPankaj Gupta #else 97*050a99a6SPankaj Gupta #error Please define CCSR SFP register endianness 98*050a99a6SPankaj Gupta #endif 99*050a99a6SPankaj Gupta 100*050a99a6SPankaj Gupta #endif/* SFP_H */ 101