1*050a99a6SPankaj Gupta /* 2*050a99a6SPankaj Gupta * Copyright 2021 NXP 3*050a99a6SPankaj Gupta * 4*050a99a6SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5*050a99a6SPankaj Gupta * 6*050a99a6SPankaj Gupta */ 7*050a99a6SPankaj Gupta 8*050a99a6SPankaj Gupta #ifndef SNVS_H 9*050a99a6SPankaj Gupta #define SNVS_H 10*050a99a6SPankaj Gupta 11*050a99a6SPankaj Gupta 12*050a99a6SPankaj Gupta #ifndef __ASSEMBLER__ 13*050a99a6SPankaj Gupta 14*050a99a6SPankaj Gupta #include <endian.h> 15*050a99a6SPankaj Gupta #include <stdbool.h> 16*050a99a6SPankaj Gupta 17*050a99a6SPankaj Gupta #include <lib/mmio.h> 18*050a99a6SPankaj Gupta 19*050a99a6SPankaj Gupta struct snvs_regs { 20*050a99a6SPankaj Gupta uint32_t reserved1; 21*050a99a6SPankaj Gupta uint32_t hp_com; /* 0x04 SNVS_HP Command Register */ 22*050a99a6SPankaj Gupta uint32_t reserved2[3]; 23*050a99a6SPankaj Gupta uint32_t hp_stat; /* 0x14 SNVS_HP Status Register */ 24*050a99a6SPankaj Gupta }; 25*050a99a6SPankaj Gupta 26*050a99a6SPankaj Gupta #ifdef NXP_SNVS_BE 27*050a99a6SPankaj Gupta #define snvs_read32(a) bswap32(mmio_read_32((uintptr_t)(a))) 28*050a99a6SPankaj Gupta #define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), bswap32((v))) 29*050a99a6SPankaj Gupta #elif defined(NXP_SNVS_LE) 30*050a99a6SPankaj Gupta #define snvs_read32(a) mmio_read_32((uintptr_t)(a)) 31*050a99a6SPankaj Gupta #define snvs_write32(a, v) mmio_write_32((uintptr_t)(a), (v)) 32*050a99a6SPankaj Gupta #else 33*050a99a6SPankaj Gupta #error Please define CCSR SNVS register endianness 34*050a99a6SPankaj Gupta #endif 35*050a99a6SPankaj Gupta 36*050a99a6SPankaj Gupta void snvs_init(uintptr_t nxp_snvs_addr); 37*050a99a6SPankaj Gupta uint32_t get_snvs_state(void); 38*050a99a6SPankaj Gupta void transition_snvs_non_secure(void); 39*050a99a6SPankaj Gupta void transition_snvs_soft_fail(void); 40*050a99a6SPankaj Gupta uint32_t transition_snvs_trusted(void); 41*050a99a6SPankaj Gupta uint32_t transition_snvs_secure(void); 42*050a99a6SPankaj Gupta 43*050a99a6SPankaj Gupta uint32_t snvs_read_lp_gpr_bit(uint32_t offset, uint32_t bit_pos); 44*050a99a6SPankaj Gupta void snvs_write_lp_gpr_bit(uint32_t offset, uint32_t bit_pos, bool flag_val); 45*050a99a6SPankaj Gupta 46*050a99a6SPankaj Gupta void snvs_disable_zeroize_lp_gpr(void); 47*050a99a6SPankaj Gupta 48*050a99a6SPankaj Gupta #if defined(NXP_NV_SW_MAINT_LAST_EXEC_DATA) && defined(NXP_COINED_BB) 49*050a99a6SPankaj Gupta uint32_t snvs_read_app_data(void); 50*050a99a6SPankaj Gupta uint32_t snvs_read_app_data_bit(uint32_t bit_pos); 51*050a99a6SPankaj Gupta void snvs_clear_app_data(void); 52*050a99a6SPankaj Gupta void snvs_write_app_data_bit(uint32_t bit_pos); 53*050a99a6SPankaj Gupta #endif 54*050a99a6SPankaj Gupta 55*050a99a6SPankaj Gupta #endif /* __ASSEMBLER__ */ 56*050a99a6SPankaj Gupta 57*050a99a6SPankaj Gupta /* SSM_ST field in SNVS status reg */ 58*050a99a6SPankaj Gupta #define HPSTS_CHECK_SSM_ST 0x900 /* SNVS is in check state */ 59*050a99a6SPankaj Gupta #define HPSTS_NON_SECURE_SSM_ST 0xb00 /* SNVS is in non secure state */ 60*050a99a6SPankaj Gupta #define HPSTS_TRUST_SSM_ST 0xd00 /* SNVS is in trusted state */ 61*050a99a6SPankaj Gupta #define HPSTS_SECURE_SSM_ST 0xf00 /* SNVS is in secure state */ 62*050a99a6SPankaj Gupta #define HPSTS_SOFT_FAIL_SSM_ST 0x300 /* SNVS is in soft fail state */ 63*050a99a6SPankaj Gupta #define HPSTS_MASK_SSM_ST 0xf00 /* SSM_ST field mask in SNVS reg */ 64*050a99a6SPankaj Gupta 65*050a99a6SPankaj Gupta /* SNVS register bits */ 66*050a99a6SPankaj Gupta #define HPCOM_SW_SV 0x100 /* Security Violation bit */ 67*050a99a6SPankaj Gupta #define HPCOM_SW_FSV 0x200 /* Fatal Security Violation bit */ 68*050a99a6SPankaj Gupta #define HPCOM_SSM_ST 0x1 /* SSM_ST field in SNVS command reg */ 69*050a99a6SPankaj Gupta #define HPCOM_SSM_ST_DIS 0x2 /* Disable Secure to Trusted State */ 70*050a99a6SPankaj Gupta #define HPCOM_SSM_SFNS_DIS 0x4 /* Disable Soft Fail to Non-Secure */ 71*050a99a6SPankaj Gupta 72*050a99a6SPankaj Gupta #define NXP_LP_GPR0_OFFSET 0x90 73*050a99a6SPankaj Gupta #define NXP_LPCR_OFFSET 0x38 74*050a99a6SPankaj Gupta #define NXP_GPR_Z_DIS_BIT 24 75*050a99a6SPankaj Gupta 76*050a99a6SPankaj Gupta #ifdef NXP_COINED_BB 77*050a99a6SPankaj Gupta 78*050a99a6SPankaj Gupta #ifndef NXP_APP_DATA_LP_GPR_OFFSET 79*050a99a6SPankaj Gupta #define NXP_APP_DATA_LP_GPR_OFFSET NXP_LP_GPR0_OFFSET 80*050a99a6SPankaj Gupta #endif 81*050a99a6SPankaj Gupta 82*050a99a6SPankaj Gupta #define NXP_LPGPR_ZEROTH_BIT 0 83*050a99a6SPankaj Gupta 84*050a99a6SPankaj Gupta #endif /* NXP_COINED_BB */ 85*050a99a6SPankaj Gupta 86*050a99a6SPankaj Gupta #endif /* SNVS_H */ 87