1*050a99a6SPankaj Gupta /* 2*050a99a6SPankaj Gupta * Copyright 2021 NXP 3*050a99a6SPankaj Gupta * 4*050a99a6SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5*050a99a6SPankaj Gupta * 6*050a99a6SPankaj Gupta */ 7*050a99a6SPankaj Gupta 8*050a99a6SPankaj Gupta #ifndef QSPI_H 9*050a99a6SPankaj Gupta #define QSPI_H 10*050a99a6SPankaj Gupta 11*050a99a6SPankaj Gupta #include <endian.h> 12*050a99a6SPankaj Gupta #include <lib/mmio.h> 13*050a99a6SPankaj Gupta 14*050a99a6SPankaj Gupta #define CHS_QSPI_MCR 0x01550000 15*050a99a6SPankaj Gupta #define CHS_QSPI_64LE 0xC 16*050a99a6SPankaj Gupta 17*050a99a6SPankaj Gupta #ifdef NXP_QSPI_BE 18*050a99a6SPankaj Gupta #define qspi_in32(a) bswap32(mmio_read_32((uintptr_t)(a))) 19*050a99a6SPankaj Gupta #define qspi_out32(a, v) mmio_write_32((uintptr_t)(a), bswap32(v)) 20*050a99a6SPankaj Gupta #elif defined(NXP_QSPI_LE) 21*050a99a6SPankaj Gupta #define qspi_in32(a) mmio_read_32((uintptr_t)(a)) 22*050a99a6SPankaj Gupta #define qspi_out32(a, v) mmio_write_32((uintptr_t)(a), (v)) 23*050a99a6SPankaj Gupta #else 24*050a99a6SPankaj Gupta #error Please define CCSR QSPI register endianness 25*050a99a6SPankaj Gupta #endif 26*050a99a6SPankaj Gupta 27*050a99a6SPankaj Gupta int qspi_io_setup(uintptr_t nxp_qspi_flash_addr, 28*050a99a6SPankaj Gupta size_t nxp_qspi_flash_size, 29*050a99a6SPankaj Gupta uintptr_t fip_offset); 30*050a99a6SPankaj Gupta #endif /* __QSPI_H__ */ 31