1*050a99a6SPankaj Gupta /* 2*050a99a6SPankaj Gupta * Copyright 2021 NXP 3*050a99a6SPankaj Gupta * 4*050a99a6SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5*050a99a6SPankaj Gupta * 6*050a99a6SPankaj Gupta */ 7*050a99a6SPankaj Gupta 8*050a99a6SPankaj Gupta #ifndef PMU_H 9*050a99a6SPankaj Gupta #define PMU_H 10*050a99a6SPankaj Gupta 11*050a99a6SPankaj Gupta /* PMU Registers' OFFSET */ 12*050a99a6SPankaj Gupta #define PMU_PCPW20SR_OFFSET 0x830 13*050a99a6SPankaj Gupta #define PMU_CLL2FLUSHSETR_OFFSET 0x1110 14*050a99a6SPankaj Gupta #define PMU_CLSL2FLUSHCLRR_OFFSET 0x1114 15*050a99a6SPankaj Gupta #define PMU_CLL2FLUSHSR_OFFSET 0x1118 16*050a99a6SPankaj Gupta #define PMU_POWMGTCSR_VAL (1 << 20) 17*050a99a6SPankaj Gupta 18*050a99a6SPankaj Gupta /* PMU Registers */ 19*050a99a6SPankaj Gupta #define CORE_TIMEBASE_ENBL_OFFSET 0x8A0 20*050a99a6SPankaj Gupta #define CLUST_TIMER_BASE_ENBL_OFFSET 0x18A0 21*050a99a6SPankaj Gupta 22*050a99a6SPankaj Gupta #define PMU_IDLE_CLUSTER_MASK 0x2 23*050a99a6SPankaj Gupta #define PMU_FLUSH_CLUSTER_MASK 0x2 24*050a99a6SPankaj Gupta #define PMU_IDLE_CORE_MASK 0xfe 25*050a99a6SPankaj Gupta 26*050a99a6SPankaj Gupta /* pmu register offsets and bitmaps */ 27*050a99a6SPankaj Gupta #define PMU_POWMGTDCR0_OFFSET 0xC20 28*050a99a6SPankaj Gupta #define PMU_POWMGTCSR_OFFSET 0x4000 29*050a99a6SPankaj Gupta #define PMU_CLAINACTSETR_OFFSET 0x1100 30*050a99a6SPankaj Gupta #define PMU_CLAINACTCLRR_OFFSET 0x1104 31*050a99a6SPankaj Gupta #define PMU_CLSINACTSETR_OFFSET 0x1108 32*050a99a6SPankaj Gupta #define PMU_CLSINACTCLRR_OFFSET 0x110C 33*050a99a6SPankaj Gupta #define PMU_CLL2FLUSHSETR_OFFSET 0x1110 34*050a99a6SPankaj Gupta #define PMU_CLL2FLUSHCLRR_OFFSET 0x1114 35*050a99a6SPankaj Gupta #define PMU_IPPDEXPCR0_OFFSET 0x4040 36*050a99a6SPankaj Gupta #define PMU_IPPDEXPCR1_OFFSET 0x4044 37*050a99a6SPankaj Gupta #define PMU_IPPDEXPCR2_OFFSET 0x4048 38*050a99a6SPankaj Gupta #define PMU_IPPDEXPCR3_OFFSET 0x404C 39*050a99a6SPankaj Gupta #define PMU_IPPDEXPCR4_OFFSET 0x4050 40*050a99a6SPankaj Gupta #define PMU_IPPDEXPCR5_OFFSET 0x4054 41*050a99a6SPankaj Gupta #define PMU_IPPDEXPCR6_OFFSET 0x4058 42*050a99a6SPankaj Gupta #define PMU_IPSTPCR0_OFFSET 0x4120 43*050a99a6SPankaj Gupta #define PMU_IPSTPCR1_OFFSET 0x4124 44*050a99a6SPankaj Gupta #define PMU_IPSTPCR2_OFFSET 0x4128 45*050a99a6SPankaj Gupta #define PMU_IPSTPCR3_OFFSET 0x412C 46*050a99a6SPankaj Gupta #define PMU_IPSTPCR4_OFFSET 0x4130 47*050a99a6SPankaj Gupta #define PMU_IPSTPCR5_OFFSET 0x4134 48*050a99a6SPankaj Gupta #define PMU_IPSTPCR6_OFFSET 0x4138 49*050a99a6SPankaj Gupta #define PMU_IPSTPACKSR0_OFFSET 0x4140 50*050a99a6SPankaj Gupta #define PMU_IPSTPACKSR1_OFFSET 0x4144 51*050a99a6SPankaj Gupta #define PMU_IPSTPACKSR2_OFFSET 0x4148 52*050a99a6SPankaj Gupta #define PMU_IPSTPACKSR3_OFFSET 0x414C 53*050a99a6SPankaj Gupta #define PMU_IPSTPACKSR4_OFFSET 0x4150 54*050a99a6SPankaj Gupta #define PMU_IPSTPACKSR5_OFFSET 0x4154 55*050a99a6SPankaj Gupta #define PMU_IPSTPACKSR6_OFFSET 0x4158 56*050a99a6SPankaj Gupta 57*050a99a6SPankaj Gupta #define CLAINACT_DISABLE_ACP 0xFF 58*050a99a6SPankaj Gupta #define CLSINACT_DISABLE_SKY 0xFF 59*050a99a6SPankaj Gupta #define POWMGTDCR_STP_OV_EN 0x1 60*050a99a6SPankaj Gupta #define POWMGTCSR_LPM20_REQ 0x00100000 61*050a99a6SPankaj Gupta 62*050a99a6SPankaj Gupta /* Used by PMU */ 63*050a99a6SPankaj Gupta #define DEVDISR1_MASK 0x024F3504 64*050a99a6SPankaj Gupta #define DEVDISR2_MASK 0x0003FFFF 65*050a99a6SPankaj Gupta #define DEVDISR3_MASK 0x0000303F 66*050a99a6SPankaj Gupta #define DEVDISR4_MASK 0x0000FFFF 67*050a99a6SPankaj Gupta #define DEVDISR5_MASK 0x00F07603 68*050a99a6SPankaj Gupta #define DEVDISR6_MASK 0x00000001 69*050a99a6SPankaj Gupta 70*050a99a6SPankaj Gupta #ifndef __ASSEMBLER__ 71*050a99a6SPankaj Gupta void enable_timer_base_to_cluster(uintptr_t nxp_pmu_addr); 72*050a99a6SPankaj Gupta void enable_core_tb(uintptr_t nxp_pmu_addr); 73*050a99a6SPankaj Gupta #endif /* __ASSEMBLER__ */ 74*050a99a6SPankaj Gupta 75*050a99a6SPankaj Gupta #endif 76