1*28279cf2SJiafei Pan /* 2*28279cf2SJiafei Pan * Copyright 2022 NXP 3*28279cf2SJiafei Pan * 4*28279cf2SJiafei Pan * SPDX-License-Identifier: BSD-3-Clause 5*28279cf2SJiafei Pan */ 6*28279cf2SJiafei Pan 7*28279cf2SJiafei Pan #ifndef IFC_NAND_H 8*28279cf2SJiafei Pan #define IFC_NAND_H 9*28279cf2SJiafei Pan 10*28279cf2SJiafei Pan #define NXP_IFC_SRAM_BUFFER_SIZE UL(0x100000) /* 1M */ 11*28279cf2SJiafei Pan 12*28279cf2SJiafei Pan int ifc_nand_init(uintptr_t *block_dev_spec, 13*28279cf2SJiafei Pan uintptr_t ifc_region_addr, 14*28279cf2SJiafei Pan uintptr_t ifc_register_addr, 15*28279cf2SJiafei Pan size_t ifc_sram_size, 16*28279cf2SJiafei Pan uintptr_t ifc_nand_blk_offset, 17*28279cf2SJiafei Pan size_t ifc_nand_blk_size); 18*28279cf2SJiafei Pan 19*28279cf2SJiafei Pan #endif /*IFC_NAND_H*/ 20