1b525a8f0SKuldeep Singh // SPDX-License-Identifier: BSD-3-Clause 2b525a8f0SKuldeep Singh /* 3a4f5015aSJiafei Pan * Copyright 2020-2021 NXP 4b525a8f0SKuldeep Singh */ 5b525a8f0SKuldeep Singh 6b525a8f0SKuldeep Singh /** 7b525a8f0SKuldeep Singh * @Flash info 8b525a8f0SKuldeep Singh * 9b525a8f0SKuldeep Singh */ 10b525a8f0SKuldeep Singh #ifndef FLASH_INFO_H 11b525a8f0SKuldeep Singh #define FLASH_INFO_H 12b525a8f0SKuldeep Singh 13b525a8f0SKuldeep Singh #define SZ_16M_BYTES 0x1000000U 14b525a8f0SKuldeep Singh 15*1ff7e46bSPankaj Gupta /* Start of "if defined(CONFIG_MT25QU512A)" */ 16b525a8f0SKuldeep Singh #if defined(CONFIG_MT25QU512A) 17b525a8f0SKuldeep Singh #define F_SECTOR_64K 0x10000U 18b525a8f0SKuldeep Singh #define F_PAGE_256 0x100U 19b525a8f0SKuldeep Singh #define F_SECTOR_4K 0x1000U 20b525a8f0SKuldeep Singh #define F_FLASH_SIZE_BYTES 0x4000000U 21b525a8f0SKuldeep Singh #define F_SECTOR_ERASE_SZ F_SECTOR_64K 22b525a8f0SKuldeep Singh #ifdef CONFIG_FSPI_4K_ERASE 23b525a8f0SKuldeep Singh #define F_SECTOR_ERASE_SZ F_SECTOR_4K 24b525a8f0SKuldeep Singh #endif 25b525a8f0SKuldeep Singh 26*1ff7e46bSPankaj Gupta /* End of "if defined(CONFIG_MT25QU512A)" */ 27*1ff7e46bSPankaj Gupta 28*1ff7e46bSPankaj Gupta /* Start of "if defined(CONFIG_MX25U25645G)" */ 29b525a8f0SKuldeep Singh #elif defined(CONFIG_MX25U25645G) 30b525a8f0SKuldeep Singh #define F_SECTOR_64K 0x10000U 31b525a8f0SKuldeep Singh #define F_PAGE_256 0x100U 32b525a8f0SKuldeep Singh #define F_SECTOR_4K 0x1000U 33b525a8f0SKuldeep Singh #define F_FLASH_SIZE_BYTES 0x2000000U 34b525a8f0SKuldeep Singh #define F_SECTOR_ERASE_SZ F_SECTOR_64K 35b525a8f0SKuldeep Singh #ifdef CONFIG_FSPI_4K_ERASE 36b525a8f0SKuldeep Singh #define F_SECTOR_ERASE_SZ F_SECTOR_4K 37b525a8f0SKuldeep Singh #endif 38b525a8f0SKuldeep Singh 39*1ff7e46bSPankaj Gupta /* End of "if defined(CONFIG_MX25U25645G)" */ 40*1ff7e46bSPankaj Gupta 41*1ff7e46bSPankaj Gupta /* Start of "if defined(CONFIG_MX25U51245G)" */ 42b525a8f0SKuldeep Singh #elif defined(CONFIG_MX25U51245G) 43b525a8f0SKuldeep Singh #define F_SECTOR_64K 0x10000U 44b525a8f0SKuldeep Singh #define F_PAGE_256 0x100U 45b525a8f0SKuldeep Singh #define F_SECTOR_4K 0x1000U 46b525a8f0SKuldeep Singh #define F_FLASH_SIZE_BYTES 0x4000000U 47b525a8f0SKuldeep Singh #define F_SECTOR_ERASE_SZ F_SECTOR_64K 48b525a8f0SKuldeep Singh #ifdef CONFIG_FSPI_4K_ERASE 49b525a8f0SKuldeep Singh #define F_SECTOR_ERASE_SZ F_SECTOR_4K 50b525a8f0SKuldeep Singh #endif 51b525a8f0SKuldeep Singh 52*1ff7e46bSPankaj Gupta /* End of "if defined(CONFIG_MX25U51245G)" */ 53*1ff7e46bSPankaj Gupta 54*1ff7e46bSPankaj Gupta /* Start of "if defined(CONFIG_MT35XU512A)" */ 55b525a8f0SKuldeep Singh #elif defined(CONFIG_MT35XU512A) 56b525a8f0SKuldeep Singh #define F_SECTOR_128K 0x20000U 57b525a8f0SKuldeep Singh #define F_SECTOR_32K 0x8000U 58b525a8f0SKuldeep Singh #define F_PAGE_256 0x100U 59b525a8f0SKuldeep Singh #define F_SECTOR_4K 0x1000U 60b525a8f0SKuldeep Singh #define F_FLASH_SIZE_BYTES 0x4000000U 61b525a8f0SKuldeep Singh #define F_SECTOR_ERASE_SZ F_SECTOR_128K 62b525a8f0SKuldeep Singh #ifdef CONFIG_FSPI_4K_ERASE 63b525a8f0SKuldeep Singh #define F_SECTOR_ERASE_SZ F_SECTOR_4K 64b525a8f0SKuldeep Singh #endif 65*1ff7e46bSPankaj Gupta /* If Warm boot is enabled for the platform, 66*1ff7e46bSPankaj Gupta * count of arm instruction N-OP(s) to mark 67*1ff7e46bSPankaj Gupta * the completion of write operation to flash; 68*1ff7e46bSPankaj Gupta * varies from one flash to other. 69*1ff7e46bSPankaj Gupta */ 70*1ff7e46bSPankaj Gupta #ifdef NXP_WARM_BOOT 71*1ff7e46bSPankaj Gupta #define FLASH_WR_COMP_WAIT_BY_NOP_COUNT 0x20000 72*1ff7e46bSPankaj Gupta #endif 73b525a8f0SKuldeep Singh 74*1ff7e46bSPankaj Gupta /* End of "if defined(CONFIG_MT35XU512A)" */ 75*1ff7e46bSPankaj Gupta 76*1ff7e46bSPankaj Gupta /* Start of #elif defined(CONFIG_MT35XU02G) */ 77a4f5015aSJiafei Pan #elif defined(CONFIG_MT35XU02G) 78a4f5015aSJiafei Pan #define F_SECTOR_128K 0x20000U 79a4f5015aSJiafei Pan #define F_PAGE_256 0x100U 80a4f5015aSJiafei Pan #define F_SECTOR_4K 0x1000U 81a4f5015aSJiafei Pan #define F_FLASH_SIZE_BYTES 0x10000000U 82a4f5015aSJiafei Pan #define F_SECTOR_ERASE_SZ F_SECTOR_128K 83a4f5015aSJiafei Pan #ifdef CONFIG_FSPI_4K_ERASE 84a4f5015aSJiafei Pan #define F_SECTOR_ERASE_SZ F_SECTOR_4K 85a4f5015aSJiafei Pan #endif 86a4f5015aSJiafei Pan 87*1ff7e46bSPankaj Gupta #endif /* End of #elif defined(CONFIG_MT35XU02G) */ 88b525a8f0SKuldeep Singh 89b525a8f0SKuldeep Singh #endif /* FLASH_INFO_H */ 90