1 /* 2 * Copyright 2020-2022,2025 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DDR_INIT_H 8 #define DDR_INIT_H 9 10 #include <stdlib.h> 11 #include <string.h> 12 #include "ddr_utils.h" 13 14 #define APBONLY_MICRORESET 0x40380420U 15 #define MASTER_PLLCTRL1 0x403816F0U 16 #define MASTER_PLLTESTMODE 0x40381708U 17 #define MASTER_PLLCTRL4 0x4038171CU 18 #define MASTER_PLLCTRL2 0x403816DCU 19 20 #define MASTER_CALOFFSET 0x40381514U 21 #define MASTER_CALMISC2 0x40381660U 22 23 #define CALDRV 0x9U 24 #define CALDRV_OFFSET 0x6U 25 #define CALDRV2_OFFSET 0xAU 26 #define CALDRV_MASK 0x3FC0U 27 28 #define CALMISC2 0x1U 29 #define CALMISC2_OFFSET 0xDU 30 31 #define PLLCTRL1_VALUE 0x00000021U 32 #define PLLTESTMODE_VALUE 0x00000024U 33 #define PLLCTRL4_VALUE 0x0000017FU 34 35 static inline uint32_t pllctrl2_value(uint16_t freq) 36 { 37 if (freq < 469U) { 38 return 0x7U; 39 } else if (freq < 625U) { 40 return 0x6U; 41 } else if (freq <= 937U) { 42 return 0xbU; 43 } else if (freq < 1250U) { 44 return 0xaU; 45 } else { 46 return 0x19U; 47 } 48 } 49 50 /* 51 * Updates PHY internal PLL settings. 52 * @param frequency - selected DDR frequency 53 */ 54 void set_optimal_pll(uint16_t frequency); 55 56 #endif /* DDR_INIT_H */ 57