1*050a99a6SPankaj Gupta /* 2*050a99a6SPankaj Gupta * Copyright 2021 NXP 3*050a99a6SPankaj Gupta * 4*050a99a6SPankaj Gupta * SPDX-License-Identifier: BSD-3-Clause 5*050a99a6SPankaj Gupta * 6*050a99a6SPankaj Gupta */ 7*050a99a6SPankaj Gupta 8*050a99a6SPankaj Gupta #ifndef DDR_OPTS_H 9*050a99a6SPankaj Gupta #define DDR_OPTS_H 10*050a99a6SPankaj Gupta 11*050a99a6SPankaj Gupta #define SDRAM_TYPE_DDR4 5 /* sdram_cfg register */ 12*050a99a6SPankaj Gupta 13*050a99a6SPankaj Gupta #define DDR_BC4 4 /* burst chop */ 14*050a99a6SPankaj Gupta #define DDR_OTF 6 /* on-the-fly BC4 and BL8 */ 15*050a99a6SPankaj Gupta #define DDR_BL8 8 /* burst length 8 */ 16*050a99a6SPankaj Gupta 17*050a99a6SPankaj Gupta #define DDR4_RTT_OFF 0 18*050a99a6SPankaj Gupta #define DDR4_RTT_60_OHM 1 /* RZQ/4 */ 19*050a99a6SPankaj Gupta #define DDR4_RTT_120_OHM 2 /* RZQ/2 */ 20*050a99a6SPankaj Gupta #define DDR4_RTT_40_OHM 3 /* RZQ/6 */ 21*050a99a6SPankaj Gupta #define DDR4_RTT_240_OHM 4 /* RZQ/1 */ 22*050a99a6SPankaj Gupta #define DDR4_RTT_48_OHM 5 /* RZQ/5 */ 23*050a99a6SPankaj Gupta #define DDR4_RTT_80_OHM 6 /* RZQ/3 */ 24*050a99a6SPankaj Gupta #define DDR4_RTT_34_OHM 7 /* RZQ/7 */ 25*050a99a6SPankaj Gupta #define DDR4_RTT_WR_OFF 0 26*050a99a6SPankaj Gupta #define DDR4_RTT_WR_120_OHM 1 27*050a99a6SPankaj Gupta #define DDR4_RTT_WR_240_OHM 2 28*050a99a6SPankaj Gupta #define DDR4_RTT_WR_HZ 3 29*050a99a6SPankaj Gupta #define DDR4_RTT_WR_80_OHM 4 30*050a99a6SPankaj Gupta #define DDR_ODT_NEVER 0x0 31*050a99a6SPankaj Gupta #define DDR_ODT_CS 0x1 32*050a99a6SPankaj Gupta #define DDR_ODT_ALL_OTHER_CS 0x2 33*050a99a6SPankaj Gupta #define DDR_ODT_OTHER_DIMM 0x3 34*050a99a6SPankaj Gupta #define DDR_ODT_ALL 0x4 35*050a99a6SPankaj Gupta #define DDR_ODT_SAME_DIMM 0x5 36*050a99a6SPankaj Gupta #define DDR_ODT_CS_AND_OTHER_DIMM 0x6 37*050a99a6SPankaj Gupta #define DDR_ODT_OTHER_CS_ONSAMEDIMM 0x7 38*050a99a6SPankaj Gupta #define DDR_BA_INTLV_CS01 0x40 39*050a99a6SPankaj Gupta #define DDR_BA_INTLV_CS0123 0x64 40*050a99a6SPankaj Gupta #define DDR_BA_NONE 0 41*050a99a6SPankaj Gupta #define DDR_256B_INTLV 0x8 42*050a99a6SPankaj Gupta 43*050a99a6SPankaj Gupta struct memctl_opt { 44*050a99a6SPankaj Gupta int rdimm; 45*050a99a6SPankaj Gupta unsigned int dbw_cap_shift; 46*050a99a6SPankaj Gupta struct local_opts_s { 47*050a99a6SPankaj Gupta unsigned int auto_precharge; 48*050a99a6SPankaj Gupta unsigned int odt_rd_cfg; 49*050a99a6SPankaj Gupta unsigned int odt_wr_cfg; 50*050a99a6SPankaj Gupta unsigned int odt_rtt_norm; 51*050a99a6SPankaj Gupta unsigned int odt_rtt_wr; 52*050a99a6SPankaj Gupta } cs_odt[DDRC_NUM_CS]; 53*050a99a6SPankaj Gupta int ctlr_intlv; 54*050a99a6SPankaj Gupta unsigned int ctlr_intlv_mode; 55*050a99a6SPankaj Gupta unsigned int ba_intlv; 56*050a99a6SPankaj Gupta int addr_hash; 57*050a99a6SPankaj Gupta int ecc_mode; 58*050a99a6SPankaj Gupta int ctlr_init_ecc; 59*050a99a6SPankaj Gupta int self_refresh_in_sleep; 60*050a99a6SPankaj Gupta int self_refresh_irq_en; 61*050a99a6SPankaj Gupta int dynamic_power; 62*050a99a6SPankaj Gupta /* memory data width 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */ 63*050a99a6SPankaj Gupta unsigned int data_bus_dimm; 64*050a99a6SPankaj Gupta unsigned int data_bus_used; /* on individual board */ 65*050a99a6SPankaj Gupta unsigned int burst_length; /* BC4, OTF and BL8 */ 66*050a99a6SPankaj Gupta int otf_burst_chop_en; 67*050a99a6SPankaj Gupta int mirrored_dimm; 68*050a99a6SPankaj Gupta int quad_rank_present; 69*050a99a6SPankaj Gupta int output_driver_impedance; 70*050a99a6SPankaj Gupta int ap_en; 71*050a99a6SPankaj Gupta int x4_en; 72*050a99a6SPankaj Gupta 73*050a99a6SPankaj Gupta int caslat_override; 74*050a99a6SPankaj Gupta unsigned int caslat_override_value; 75*050a99a6SPankaj Gupta int addt_lat_override; 76*050a99a6SPankaj Gupta unsigned int addt_lat_override_value; 77*050a99a6SPankaj Gupta 78*050a99a6SPankaj Gupta unsigned int clk_adj; 79*050a99a6SPankaj Gupta unsigned int cpo_sample; 80*050a99a6SPankaj Gupta unsigned int wr_data_delay; 81*050a99a6SPankaj Gupta 82*050a99a6SPankaj Gupta unsigned int cswl_override; 83*050a99a6SPankaj Gupta unsigned int wrlvl_override; 84*050a99a6SPankaj Gupta unsigned int wrlvl_sample; 85*050a99a6SPankaj Gupta unsigned int wrlvl_start; 86*050a99a6SPankaj Gupta unsigned int wrlvl_ctl_2; 87*050a99a6SPankaj Gupta unsigned int wrlvl_ctl_3; 88*050a99a6SPankaj Gupta 89*050a99a6SPankaj Gupta int half_strength_drive_en; 90*050a99a6SPankaj Gupta int twot_en; 91*050a99a6SPankaj Gupta int threet_en; 92*050a99a6SPankaj Gupta unsigned int bstopre; 93*050a99a6SPankaj Gupta unsigned int tfaw_ps; 94*050a99a6SPankaj Gupta 95*050a99a6SPankaj Gupta int rtt_override; 96*050a99a6SPankaj Gupta unsigned int rtt_override_value; 97*050a99a6SPankaj Gupta unsigned int rtt_wr_override_value; 98*050a99a6SPankaj Gupta unsigned int rtt_park; 99*050a99a6SPankaj Gupta 100*050a99a6SPankaj Gupta int auto_self_refresh_en; 101*050a99a6SPankaj Gupta unsigned int sr_it; 102*050a99a6SPankaj Gupta unsigned int ddr_cdr1; 103*050a99a6SPankaj Gupta unsigned int ddr_cdr2; 104*050a99a6SPankaj Gupta 105*050a99a6SPankaj Gupta unsigned int trwt_override; 106*050a99a6SPankaj Gupta unsigned int trwt; 107*050a99a6SPankaj Gupta unsigned int twrt; 108*050a99a6SPankaj Gupta unsigned int trrt; 109*050a99a6SPankaj Gupta unsigned int twwt; 110*050a99a6SPankaj Gupta 111*050a99a6SPankaj Gupta unsigned int vref_phy; 112*050a99a6SPankaj Gupta unsigned int vref_dimm; 113*050a99a6SPankaj Gupta unsigned int odt; 114*050a99a6SPankaj Gupta unsigned int phy_tx_impedance; 115*050a99a6SPankaj Gupta unsigned int phy_atx_impedance; 116*050a99a6SPankaj Gupta unsigned int skip2d; 117*050a99a6SPankaj Gupta }; 118*050a99a6SPankaj Gupta 119*050a99a6SPankaj Gupta #endif /* DDR_OPTS_H */ 120